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IA6805E2-PDW40I-R-00 Datasheet(PDF) 8 Page - InnovASIC, Inc

Part # IA6805E2-PDW40I-R-00
Description  Microprocessor Unit
PDF  33 Pages
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Manufacturer  INNOVASIC [InnovASIC, Inc]
Direct Link  http://www.innovasic.com
Logo INNOVASIC - InnovASIC, Inc

IA6805E2-PDW40I-R-00 Datasheet(HTML) 8 Page - InnovASIC, Inc

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IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
Registers:
The following paragraphs describe the registers contained in the MPU. Figure 6 shows the
programming model and Figure 7 shows the interrupt stacking order.
A
X
SP
1
0
0
0
0
0
0
H
I
N
Z
C
70
CC
CONDITION CODE REGISTER
CARRY/BORROW
HALF CARRY
INTERRUPT MASK
NEGATIVE
ZERO
STACK POINTER
PROGRAM COUNTER
INDEX REGISTER
ACCUMULATOR
70
12
0
7
8
PCH
PCL
12
6
0
4
0
Figure 6. Programming Model
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
CONDITION CODE
REGISTER
ACCUMULATOR
INDEX REGISTER
1
1
1
I
N
T
E
R
R
U
P
T
DECREASING MEMORY
ADDRESSES
STACK
PCH
0
0
0
PCL
R
E
T
U
R
N
INCREASING MEMORY
ADDRESSES
UNSTACK
Figure 7. Interrupt Stacking Order
Copyright © 2007
IA211081401-03
www.Innovasic.com
Customer Support:
Page 8 of 33
1-888-824-4184
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