IA6805E2-PDW40I-R-00 datasheet(13/33 Pages) INNOVASIC

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IA6805E2

29 August 2007

Microprocessor Unit

As of Production Version 00

Figure 10. Interrupt Mode Diagram

Timer Interrupt:

If the timer mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are

cleared, each time the timer decrements to zero ($01 to $00 transition) an interrupt request is

generated. When the interrupt is recognized, the current state of the machine is pushed onto

the stack and the condition code register I-bit gets set masking further interrupts until the

present one is serviced. The program counter is then loaded with the contents of the timer

interrupt vector, which contains the location of the timer interrupt service routine. The

contents of $1FF8 and $1FF9 specify the address for this service routine. If the MPU is in

the wait mode and a timer interrupt occurs, then the contents of $1FF6 and $1FF7 specify

the service routine. When the timer interrupt service routine is complete, the software

executes an RTI instruction to restore the machine state and starts executing the interrupt

program.

Software Interrupt:

Software interrupt is an executable instruction regardless of the state of the interrupt mask

bit (I) in the condition code register. SWI is similar to hardware interrupts. It executes after

the other interrupts if the interrupt mask bit is zero. The contents of $1FFC and $1FFD

specify the address for this service routine.

Low Power Modes:

The low power modes consist of the stop instruction and the wait instruction. The

following paragraphs explain these modes of operation.

IA211081401-03

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