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DSPIC30F2011AT-30E/S Datasheet(PDF) 229 Page - Microchip Technology |
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DSPIC30F2011AT-30E/S Datasheet(HTML) 229 Page - Microchip Technology |
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229 / 238 page  © 2006 Microchip Technology Inc. Preliminary DS70143C-page 227 dsPIC30F6011A/6012A/6013A/6014A INDEX A AC Characteristics ............................................................ 184 Internal FRC Jitter, Accuracy and Drift ..................... 187 Internal LPRC Accuracy............................................ 188 Load Conditions ........................................................ 184 AC Temperature and Voltage Specifications .................... 184 AC-Link Mode Operation .................................................. 130 16-bit Mode ............................................................... 130 20-bit Mode ............................................................... 130 ADC .................................................................................. 133 Aborting a Conversion .............................................. 135 ADCHS Register ....................................................... 133 ADCON1 Register..................................................... 133 ADCON2 Register..................................................... 133 ADCON3 Register..................................................... 133 ADCSSL Register ..................................................... 133 ADPCFG Register..................................................... 133 Configuring Analog Port Pins.............................. 64, 140 Connection Considerations....................................... 140 Conversion Operation ............................................... 134 Effects of a Reset...................................................... 139 Operation During CPU Idle Mode ............................. 139 Operation During CPU Sleep Mode .......................... 139 Output Formats ......................................................... 139 Power-down Modes .................................................. 139 Programming the Start of Conversion Trigger .......... 135 Register Map............................................................. 141 Result Buffer ............................................................. 134 Sampling Requirements............................................ 138 Selecting the Conversion Clock ................................ 135 Selecting the Conversion Sequence......................... 134 ADC Conversion Speeds .................................................. 136 Address Generator Units .................................................... 39 Alternate Vector Table ........................................................ 49 Analog-to-Digital Converter. See ADC. Assembler MPASM Assembler................................................... 172 Automatic Clock Stretch...................................................... 98 During 10-bit Addressing (STREN = 1)....................... 98 During 7-bit Addressing (STREN = 1)......................... 98 Receive Mode ............................................................. 98 Transmit Mode ............................................................ 98 B Band Gap Start-up Time Requirements............................................................ 191 Timing Characteristics .............................................. 191 Barrel Shifter ....................................................................... 23 Bit-Reversed Addressing .................................................... 42 Example ...................................................................... 43 Implementation ........................................................... 42 Modifier Values Table ................................................. 43 Sequence Table (16-Entry)......................................... 43 Block Diagrams 12-bit ADC Functional............................................... 133 16-bit Timer1 Module .................................................. 70 16-bit Timer2............................................................... 75 16-bit Timer3............................................................... 75 16-bit Timer4............................................................... 80 16-bit Timer5............................................................... 80 32-bit Timer2/3............................................................ 74 32-bit Timer4/5............................................................ 79 CAN Buffers and Protocol Engine............................. 112 DCI Module............................................................... 124 Dedicated Port Structure ............................................ 63 DSP Engine ................................................................ 20 dsPIC30F6011A/6012A .............................................. 10 dsPIC30F6013A/6014A .............................................. 11 External Power-on Reset Circuit .............................. 156 I2C .............................................................................. 96 Input Capture Mode.................................................... 83 Oscillator System...................................................... 145 Output Compare Mode ............................................... 87 Reset System ........................................................... 153 Shared Port Structure ................................................. 64 SPI.............................................................................. 92 SPI Master/Slave Connection..................................... 92 UART Receiver......................................................... 104 UART Transmitter..................................................... 103 BOR. See Brown-out Reset. Brown-out Reset ............................................................... 143 Characteristics.................................................. 182, 183 Timing Requirements ............................................... 190 C C Compilers MPLAB C18 .............................................................. 172 MPLAB C30 .............................................................. 172 CAN Module ..................................................................... 111 Baud Rate Setting .................................................... 116 CAN1 Register Map.................................................. 118 CAN2 Register Map.................................................. 120 Frame Types ............................................................ 111 I/O Timing Characteristics ........................................ 209 I/O Timing Requirements.......................................... 209 Message Reception.................................................. 114 Message Transmission............................................. 115 Modes of Operation .................................................. 113 Overview................................................................... 111 CLKOUT and I/O Timing Characteristics.......................................................... 188 Requirements ........................................................... 188 Code Examples Data EEPROM Block Erase ....................................... 58 Data EEPROM Block Write ........................................ 60 Data EEPROM Read.................................................. 57 Data EEPROM Word Erase ....................................... 58 Data EEPROM Word Write ........................................ 59 Erasing a Row of Program Memory ........................... 53 Initiating a Programming Sequence ........................... 54 Loading Write Latches ................................................ 54 Code Protection ................................................................ 143 Core Architecture Overview..................................................................... 15 CPU Architecture Overview ................................................ 15 Customer Change Notification Service............................. 233 Customer Notification Service .......................................... 233 Customer Support............................................................. 233 D Data Accumulators and Adder/Subtractor .......................... 21 Data Space Write Saturation ...................................... 23 Overflow and Saturation ............................................. 21 Round Logic ............................................................... 22 Write Back .................................................................. 22 Data Address Space........................................................... 31 Alignment.................................................................... 34 Alignment (Figure) ...................................................... 35 Effect of Invalid Memory Accesses (Table) ................ 34 |
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