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DSPIC30F2011AT-30E/S Datasheet(PDF) 233 Page - Microchip Technology |
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DSPIC30F2011AT-30E/S Datasheet(HTML) 233 Page - Microchip Technology |
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233 / 238 page  © 2006 Microchip Technology Inc. Preliminary DS70143C-page 231 dsPIC30F6011A/6012A/6013A/6014A SPI Module ......................................................................... 91 Framed SPI Support ................................................... 91 Operating Function Description .................................. 91 Operation During CPU Idle Mode ............................... 93 Operation During CPU Sleep Mode ............................ 93 SDOx Disable ............................................................. 91 Slave Select Synchronization ..................................... 93 SPI1 Register Map...................................................... 94 SPI2 Register Map...................................................... 94 Timing Characteristics Master Mode (CKE = 0) .................................... 199 Master Mode (CKE = 1) .................................... 200 Slave Mode (CKE = 1) .............................. 201, 203 Timing Requirements Master Mode (CKE = 0) .................................... 199 Master Mode (CKE = 1) .................................... 201 Slave Mode (CKE = 0) ...................................... 202 Slave Mode (CKE = 1) ...................................... 204 Word and Byte Communication .................................. 91 STATUS Register ............................................................... 16 Symbols used in Opcode Descriptions ............................. 164 System Integration ............................................................ 143 Register Map for dsPIC30F601xA ............................ 161 T Table Instruction Operation Summary ................................ 51 Temperature and Voltage Specifications AC ............................................................................. 184 Timer1 Module .................................................................... 69 16-bit Asynchronous Counter Mode ........................... 69 16-bit Synchronous Counter Mode ............................. 69 16-bit Timer Mode ....................................................... 69 Gate Operation ........................................................... 70 Interrupt....................................................................... 71 Operation During Sleep Mode .................................... 70 Prescaler..................................................................... 70 Real-Time Clock ......................................................... 71 Interrupts............................................................. 71 Oscillator Operation ............................................ 71 Register Map............................................................... 72 Timer2 and Timer3 Selection Mode .................................... 88 Timer2/3 Module ................................................................. 73 16-bit Timer Mode ....................................................... 73 32-bit Synchronous Counter Mode ............................. 73 32-bit Timer Mode ....................................................... 73 ADC Event Trigger...................................................... 76 Gate Operation ........................................................... 76 Interrupt....................................................................... 76 Operation During Sleep Mode .................................... 76 Register Map............................................................... 77 Timer Prescaler........................................................... 76 Timer4/5 Module ................................................................. 79 Register Map............................................................... 81 Timing Characteristics ADC Low-speed (ASAM = 0, SSRC = 000) .............. 212 Band Gap Start-up Time ........................................... 191 CAN Module I/O........................................................ 209 CLKOUT and I/O....................................................... 188 DCI Module AC-Link Mode ................................................... 198 Multichannel, I2S Modes ................................... 196 External Clock........................................................... 184 I2C Bus Data Master Mode ..................................................... 205 Slave Mode ....................................................... 207 I2C Bus Start/Stop Bits Master Mode..................................................... 205 Slave Mode ...................................................... 207 Input Capture (CAPX)............................................... 194 OC/PWM Module...................................................... 195 Oscillator Start-up Timer........................................... 189 Output Compare Module .......................................... 194 Power-up Timer ........................................................ 189 Reset ........................................................................ 189 SPI Module Master Mode (CKE = 0).................................... 199 Master Mode (CKE = 1).................................... 200 Slave Mode (CKE = 0)...................................... 201 Slave Mode (CKE = 1)...................................... 203 Type A, B and C Timer External Clock ..................... 192 Watchdog Timer (WDT)............................................ 189 Timing Diagrams CAN Bit..................................................................... 116 Frame Sync, AC-Link Start of Frame ....................... 126 Frame Sync, Multi-Channel Mode ............................ 126 I2S Interface Frame Sync ......................................... 126 PWM Output ............................................................... 89 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1.................................. 154 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2.................................. 155 Time-out Sequence on Power-up (MCLR Tied to VDD)...................................................... 154 Timing Diagrams.See Timing Characteristics Timing Requirements Band Gap Start-up Time........................................... 191 Brown-out Reset....................................................... 190 CAN Module I/O ....................................................... 209 CLKOUT and I/O ...................................................... 188 DCI Module AC-Link Mode................................................... 198 Multichannel, I2S Modes................................... 197 External Clock .......................................................... 185 I2C Bus Data (Master Mode) .................................... 206 I2C Bus Data (Slave Mode) ...................................... 208 Input Capture............................................................ 194 Oscillator Start-up Timer........................................... 190 Output Compare Module .......................................... 194 Power-up Timer ........................................................ 190 Reset ........................................................................ 190 Simple OC/PWM Mode ............................................ 195 SPI Module Master Mode (CKE = 0).................................... 199 Master Mode (CKE = 1).................................... 201 Slave Mode (CKE = 0)...................................... 202 Slave Mode (CKE = 1)...................................... 204 Type A Timer External Clock .................................... 192 Type B Timer External Clock .................................... 193 Type C Timer External Clock.................................... 193 Watchdog Timer (WDT)............................................ 190 Timing Specifications External Clock Requirements ................................... 185 PLL Clock ................................................................. 186 PLL Jitter .................................................................. 186 |
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