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DSPIC30F2011AT-30E/S Datasheet(PDF) 231 Page - Microchip Technology |
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DSPIC30F2011AT-30E/S Datasheet(HTML) 231 Page - Microchip Technology |
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231 / 238 page  © 2006 Microchip Technology Inc. Preliminary DS70143C-page 229 dsPIC30F6011A/6012A/6013A/6014A I I/O Pin Specifications Input .......................................................................... 181 Output ....................................................................... 181 I/O Ports .............................................................................. 63 Parallel (PIO) .............................................................. 63 I2C 10-bit Slave Mode Operation ........................................ 97 Reception.................................................................... 98 Transmission............................................................... 97 I2C 7-bit Slave Mode Operation .......................................... 97 Reception.................................................................... 97 Transmission............................................................... 97 I2C Master Mode Operation ................................................ 99 Baud Rate Generator................................................ 100 Clock Arbitration........................................................ 100 Multi-Master Communication, Bus Collision and Bus Arbitration .................................................. 100 Reception.................................................................... 99 Transmission............................................................... 99 I2C Master Mode Support ................................................... 99 I2C Module .......................................................................... 95 Addresses ................................................................... 97 Bus Data Timing Characteristics Master Mode ..................................................... 205 Slave Mode ....................................................... 207 Bus Data Timing Requirements Master Mode ..................................................... 206 Slave Mode ....................................................... 208 Bus Start/Stop Bits Timing Characteristics Master Mode ..................................................... 205 Slave Mode ....................................................... 207 General Call Address Support .................................... 99 Interrupts..................................................................... 98 IPMI Support ............................................................... 99 Operating Function Description .................................. 95 Operation During CPU Sleep and Idle Modes .......... 100 Pin Configuration ........................................................ 95 Programmer’s Model................................................... 95 Register Map............................................................. 101 Registers..................................................................... 95 Slope Control .............................................................. 99 Software Controlled Clock Stretching (STREN = 1) ....................................................... 98 Various Modes ............................................................ 95 I2S Mode Operation .......................................................... 131 Data Justification....................................................... 131 Frame and Data Word Length Selection................... 131 Idle Current (IIDLE) ............................................................ 178 In-Circuit Debugger (ICD 2) .............................................. 160 In-Circuit Serial Programming (ICSP) ......................... 51, 143 Initialization Condition for RCON Register Case 1 ........... 157 Initialization Condition for RCON Register Case 2 ........... 157 Input Capture (CAPX) Timing Characteristics .................. 194 Input Capture Module ......................................................... 83 Interrupts..................................................................... 84 Register Map............................................................... 85 Input Capture Operation During Sleep and Idle Modes ...... 84 CPU Idle Mode............................................................ 84 CPU Sleep Mode ........................................................ 84 Input Capture Timing Requirements ................................. 194 Input Change Notification Module ....................................... 67 Register Map for dsPIC30F6011A/6012 A (Bits 7-0) ............................................................. 67 Register Map for dsPIC30F6011A/6012A (Bits 15-8) ........................................................... 67 Register Map for dsPIC30F6013A/6014A (Bits 15-8) ........................................................... 67 Register Map for dsPIC30F6013A/6014A (Bits 7-0) ............................................................. 67 Instruction Addressing Modes ............................................ 39 File Register Instructions ............................................ 39 Fundamental Modes Supported ................................. 39 MAC Instructions ........................................................ 40 MCU Instructions ........................................................ 39 Move and Accumulator Instructions ........................... 40 Other Instructions ....................................................... 40 Instruction Set Overview................................................................... 166 Summary .................................................................. 163 Internet Address ............................................................... 233 Interrupt Controller Register Map .............................................................. 50 Interrupt Priority .................................................................. 46 Interrupt Sequence ............................................................. 48 Interrupt Stack Frame ................................................. 49 Interrupts ............................................................................ 45 L Load Conditions................................................................ 184 Low Voltage Detect (LVD) ................................................ 158 Low-Voltage Detect Characteristics.................................. 181 LVDL Characteristics ........................................................ 182 M Memory Organization 1, 9, 15, 25, 39, 45, 51, 57, 63, 69, 73, 79, 83, 87, 91, 95, 103, 111, 123, 133, 163 Core Register Map ..................................................... 37 Microchip Internet Web Site.............................................. 233 Modes of Operation Disable...................................................................... 113 Initialization ............................................................... 113 Listen All Messages.................................................. 113 Listen Only................................................................ 113 Loopback .................................................................. 113 Normal Operation ..................................................... 113 Module ................................................................................ 95 Modulo Addressing ............................................................. 40 Applicability................................................................. 42 Operation Example ..................................................... 41 Start and End Address ............................................... 41 W Address Register Selection .................................... 41 MPLAB ASM30 Assembler, Linker, Librarian ................... 172 MPLAB ICD 2 In-Circuit Debugger ................................... 173 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator.................................................... 173 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator.................................................... 173 MPLAB Integrated Development Environment Software ................................................................... 171 MPLAB PM3 Device Programmer .................................... 173 MPLINK Object Linker/MPLIB Object Librarian ................ 172 N NVM Register Map .............................................................. 55 |
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