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DSPIC30F2011AT-30E/S Datasheet(PDF) 234 Page - Microchip Technology

Part # DSPIC30F2011AT-30E/S
Description  High-Performance, 16-Bit Digital Signal Controllers
PDF  238 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC30F2011AT-30E/S Datasheet(HTML) 234 Page - Microchip Technology

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dsPIC30F6011A/6012A/6013A/6014A
DS70143C-page 232
Preliminary
© 2006 Microchip Technology Inc.
Trap Vectors........................................................................ 48
Traps ................................................................................... 47
Hard and Soft .............................................................. 48
Sources ....................................................................... 47
Address Error Trap ............................................. 47
Math Error Trap................................................... 47
Oscillator Fail Trap.............................................. 48
Stack Error Trap.................................................. 48
U
UART Module
Address Detect Mode ............................................... 107
Auto Baud Support.................................................... 108
Baud Rate Generator ................................................ 107
Enabling and Setting Up ........................................... 105
Framing Error (FERR)............................................... 107
Idle Status ................................................................. 107
Loopback Mode ........................................................ 107
Operation During CPU Sleep and Idle Modes .......... 108
Overview ................................................................... 103
Parity Error (PERR) .................................................. 107
Receive Break........................................................... 107
Receive Buffer (UxRXB) ........................................... 106
Receive Buffer Overrun Error (OERR Bit) ................ 106
Receive Interrupt....................................................... 106
Receiving Data.......................................................... 106
Receiving in 8-bit or 9-bit Data Mode........................ 106
Reception Error Handling.......................................... 106
Transmit Break.......................................................... 106
Transmit Buffer (UxTXB)........................................... 105
Transmit Interrupt...................................................... 106
Transmitting Data...................................................... 105
Transmitting in 8-bit Data Mode ................................ 105
Transmitting in 9-bit Data Mode ................................ 105
UART1 Register Map ................................................ 109
UART2 Register Map ................................................ 109
UART Operation
Idle Mode .................................................................. 108
Sleep Mode ............................................................... 108
Unit ID Locations............................................................... 143
Universal Asynchronous Receiver Transmitter. See UART.
W
Wake-up from Sleep ......................................................... 143
Wake-up from Sleep and Idle.............................................. 49
Watchdog Timer (WDT) ............................................ 143, 158
Enabling and Disabling ............................................. 158
Operation .................................................................. 158
Timing Characteristics .............................................. 189
Timing Requirements ................................................ 190
WWW Address.................................................................. 233
WWW, On-Line Support........................................................ 7



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