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PIC18F4550ESOSQTP Datasheet(PDF) 406 Page - Microchip Technology |
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PIC18F4550ESOSQTP Datasheet(HTML) 406 Page - Microchip Technology |
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406 / 438 page  PIC18F2455/2550/4455/4550 DS39632E-page 404 © 2009 Microchip Technology Inc. TABLE 28-28: A/D CONVERTER CHARACTERISTICS: PIC18F2455/2550/4455/4550 (INDUSTRIAL) PIC18LF2455/2550/4455/4550 (INDUSTRIAL) FIGURE 28-23: A/D CONVERSION TIMING Param No. Symbol Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSB ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSB ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±2.0 LSB ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSB ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) —VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range (VREFH – VREFL) 1.8 3.0 — — VDD – VSS VDD – VSS V V VDD < 3.0V VDD ≥ 3.0V A21 VREFH Reference Voltage High Vss + ΔVREF —VDD V A22 VREFL Reference Voltage Low VSS —VDD - ΔVREF V A25 VAIN Analog Input Voltage VREFL —VREFH V A30 ZAIN Recommended Impedance of Analog Voltage Source —— 2.5 k Ω A50 IREF VREF Input Current(2) — — — — 5 150 μA μA During VAIN acquisition. During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source. 131 130 132 BSF ADCON0, GO Q4 A/D CLK A/D DATA ADRES ADIF GO SAMPLE OLD_DATA SAMPLING STOPPED DONE NEW_DATA (Note 2) 98 7 3 2 1 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . TCY(1) 0 TDIS |
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