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PIC18F4550ESOSQTP Datasheet(PDF) 407 Page - Microchip Technology |
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PIC18F4550ESOSQTP Datasheet(HTML) 407 Page - Microchip Technology |
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407 / 438 page ![]() © 2009 Microchip Technology Inc. DS39632E-page 405 PIC18F2455/2550/4455/4550 TABLE 28-29: A/D CONVERSION REQUIREMENTS Param No. Symbol Characteristic Min Max Units Conditions 130 TAD A/D Clock Period PIC18FXXXX 0.8 25.0(1) μsTOSC based, VREF ≥ 3.0V PIC18LFXXXX 1.4 25.0(1) μsVDD = 2.0V, TOSC based, VREF full range PIC18FXXXX — 1 μs A/D RC mode PIC18LFXXXX — 3 μsVDD = 2.0V, A/D RC mode 131 TCNV Conversion Time (not including acquisition time)(2) 11 12 TAD 132 TACQ Acquisition Time(3) 1.4 — μs-40°C to +85°C 135 TSWC Switching Time from Convert → Sample — (Note 4) 137 TDIS Discharge Time 0.2 — μs Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2: ADRES registers may be read on the following TCY cycle. 3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VSS to VDD). The source impedance (RS) on the input channels is 50 Ω. 4: On the following cycle of the device clock. |
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