AM79C970AVCW datasheet(27/219 Pages) AMD

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P R E L I M I N A R Y

AMD

Am79C970A

Note that the RXCLK pin is multiplexed with the

ERD1 pin.

RXDAT

Receive Data

Input

RXDAT is an input. Rising edges of the RXCLK signal

are used to sample the data on the RXDAT input when-

ever the RXEN input is HIGH.

Note that the RXDAT pin is multiplexed with the

ERD0 pin.

RXEN

Receive Enable

Input

RXEN is an input. When this signal is HIGH, it indicates

to the core logic that the data on the RXDAT input pin

is valid.

Note that the RXEN pin is multiplexed with the

ERD2 pin.

TXCLK

Transmit Clock

Input

TXCLK is an input, providing a clock signal for MAC ac-

tivity, both transmit and receive. Rising edges of the

TXCLK can be used to validate TXDAT output data.

Note that the TXCLK pin is multiplexed with the

ERD4 pin.

TXDAT

Transmit Data

Output

TXDAT is an output, providing the serial bit stream for

transmission, including preamble, SFD data and FCS

field, if applicable. TXDAT floats when the GPSI inter-

face is not enabled.

Note that the TXDAT pin is multiplexed with the

ERD7 pin.

TXEN

Transmit Enable

Output

TXEN is an output, providing an enable signal for trans-

mission. Data on the TXDAT pin is not valid unless the

TXEN signal is HIGH. TXEN should have an external

pull-down resistor attached (e.g. 3.3 k

Ω) to ensure the

output is held inactive until the GPSI interface

is enabled.

Note that the TXEN pin is multiplexed with the ERD6 pin.

External Address Detection Interface

EAR

External Address Reject Low

Input

The incoming frame will be checked against the inter-

nally active address detection mechanisms and the

result of this check will be ORd with the value on the

EAR pin. The EAR pin is defined as REJECT. The pin

value is “OR”ed with the internal address detection re-

sult to determine if the current frame should be accepted

or rejected.

The

EAR pin is internally pulled-up and can be left un-

connected, if the EADI interface is not used.

SFBD

Start Frame—Byte Delimiter

Output

An initial rising edge on the SFBD signal indicates that a

start of frame delimiter has been detected. The serial bit

stream will follow on the SRD signal, commencing with

the destination address field. SFBD will go high for 4 bit

times (400 ns) after detecting the second ONE in the

SFD (Start of Frame Delimiter) of a received frame.

SFBD will subsequently toggle every 400 ns (1.25 MHz

frequency) with each rising edge indicating the first bit of

each subsequent byte of the received serial bit stream.

SFBD will be inactive during frame transmission.

Note that the SFBD pin is multiplexed with the EESK

and

LED1 pins.

SRD

Serial Receive Data

Output

SRD is the decoded NRZ data from the network. This

signal can be used for external address detection. When

the 10BASE-T port is selected, transitions on SRD will

only occur during receive activity. When the AUI or GPSI

port is selected, transitions on SRD will occur during

both transmit and receive activity.

Note that the SRD pin is multiplexed with the EEDO and

LED3 pins.

SRDCLK

Serial Receive Data Clock

Output

Serial Receive Data is synchronous with reference to

SRDCLK. When the 10BASE-T port is selected, transi-

tions on SRDCLK will only occur during receive activity.

When the AUI or GPSI port is selected, transitions

on SRDCLK will occur during both transmit and

receive activity.

Note that the SRDCLK pin is multiplexed with the

LED2 pin.

IEEE 1149.1 Test Access Port Interface

TCK

Test Clock

Input

TCK is the clock input for the boundary scan test mode

operation. It can operate at a frequency of up to 10 MHz.

TCK has an internal pull-up resistor. The TCK input

AM79C970AVCW Datasheet(PDF) 27 Page - Advanced Micro Devices

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