AM79C970AVCW datasheet(92/219 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C970A

The timing diagram below assumes the default pro-

gramming of ROMTMG (1001b = 9 CLK). After reading

the first byte, the PCnet-PCI II controller reads in three

more bytes by incrementing the lower portion of the

ROM address. After the last byte is strobed in,

TRDY will

be asserted on clock 44. When the host tries to perform

a burst read of the Expansion ROM, the PCnet-PCI II

will disconnect the access at the second data phase.

19436A-43

FRAME

PAR

IRDY

TRDY

DEVSEL

STOP

ERA

ERD

EROE

ERACLK

CLK

123456789

A[15:8]

A[7:2],0,0

A[7:2],0,1

FRAME

PAR

IRDY

TRDY

DEVSEL

STOP

ERA

ERD

EROE

ERACLK

CLK

A[7:2],1,0

A[7:2],1,1

Figure 40. Expansion ROM Bus Read Sequence

The host must program the Expansion ROM Base Ad-

dress register in the PCI configuration space before the

first access to the Expansion ROM. The PCnet-PCI II

controller will not react to any access to the Expansion

ROM until both MEMEN (PCI Command register, bit 1)

and ROMEN (PCI Expansion ROM Base Address regis-

ter, bit 0) are set to ONE. After the Expansion ROM is

enabled, the PCnet-PCI II controller will claim all mem-

ory read accesses with an address between ROMBASE

and ROMBASE + 64K – 4 (ROMBASE, PCI Expansion

ROM Base Address register, bits 31–11). The address

output to the Expansion ROM is the offset from the ad-

dress on the PCI bus to ROMBASE. The PCnet-PCI II

controller aliases all accesses to the Expansion ROM of

the command types “Memory Read Multiple” and “Mem-

ory Read Line” to the basic Memory Read command.

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given to

the PCI Memory Mapped I/O Base Address register, be-

fore enabling access to the Expansion ROM. The host

must set the PCI Memory Mapped I/O Base Address

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