AM79C970AVCW datasheet(30/219 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C970A

DETAILED FUNCTIONS

Slave Bus Interface Unit

The slave bus interface unit (BIU) controls all accesses

to the PCI configuration space, the Control and Status

Registers (CSR), the Bus Configuration Registers

(BCR), the Address PROM (APROM) locations and the

Expansion ROM. The table below shows the response

of the PCnet-PCI II controller to each of the PCI com-

mands in slave mode.

Table 2. Slave Commands

C[3:0]

Command

Use

0000

Interrupt Acknowledge

Not Used

0001

Special Cycle

Not Used

0010

I/O Read

Read of CSR, BCR and APROM

0011

I/O Write

Write to CSR, BCR and APROM

0100

Reserved

0101

Reserved

0110

Memory Read

Memory Mapped I/O Read of CSR, BCR and APROM

Read of the Expansion ROM

0111

Memory Write

Memory Mapped I/O Write of CSR, BCR and APROM

Dummy Write to the Expansion ROM

1000

Reserved

1001

Reserved

1010

Configuration Read

Read of the Configuration Space

1011

Configuration Write

Write to the Configuration Space

1100

Memory Read Multiple

Aliased to Memory Read

1101

Dual Address Cycle

Not Used

1110

Memory Read Line

Aliased to Memory Read

1111

Memory Write Invalidate

Aliased to Memory Write

Slave Configuration Transfers

The host can access the PCnet-PCI II controller PCI

configuration space with a configuration read or write

command. The PCnet-PCI II controller will assert

DEVSEL during the address phase when IDSEL is as-

serted, AD[1:0] are both ZERO, and the access is a con-

figuration cycle. AD[7:2] select the DWord location in the

configuration space. The PCnet-PCI II controller ig-

nores AD[10:8], because it is a single function device.

AD[31:11] are don’t care.

The active bytes within a DWord are determined by the

byte enable signals. 8-bit, 16-bit and 32-bit transfers are

supported.

DEVSEL is asserted two clock cycles after

the host has asserted

FRAME. All configuration cycles

are of fixed length. The PCnet-PCI II controller will as-

sert

TRDY on the 4th clock of the data phase.

The PCnet-PCI II controller does not support burst

transfers for access to configuration space. When the

host keeps

FRAME asserted for a second data phase,

the PCnet-PCI II controller will disconnect the transfer.

When the host tries to access the PCI configuration

space while the automatic read of the EEPROM after

H_RESET is on-going, the PCnet-PCI II controller will

terminate the access on the PCI bus with a disconnect/

retry response.

The PCnet-PCI II controller supports fast back-to-back

transactions to different targets. This is indicated by the

Fast Back-To-Back Capable bit (PCI Status register,

bit 7), which is hardwired to ONE. The PCnet-PCI II con-

troller is capable of detecting a configuration cycle even

when its address phase immediately follows the data

phase of a transaction to a different target without any

idle state in-between. There will be no contention on

the

DEVSEL, TRDY and STOP signals, since the

PCnet-PCI II controller asserts

DEVSEL on the second

clock after

FRAME is asserted (medium timing).

AD31

—

AD11

AD10

—

AD8

AD7

—

AD2

AD1

AD0

Don’t care

DWord index

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