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PIC18F4550ESOSQTP Datasheet(PDF) 423 Page - Microchip Technology |
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PIC18F4550ESOSQTP Datasheet(HTML) 423 Page - Microchip Technology |
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423 / 430 page  © 2007 Microchip Technology Inc. Preliminary DS39632D-page 421 PIC18F2455/2550/4455/4550 Oscillator .......................................................... 129, 131 Layout Considerations ..................................... 132 Low-Power Option ........................................... 131 Using Timer1 as a Clock Source ..................... 131 Overflow Interrupt .................................................... 129 Resetting, Using a Special Event Trigger Output (CCP) ....................................... 132 Special Event Trigger (ECCP) ................................. 150 TMR1H Register ...................................................... 129 TMR1L Register ....................................................... 129 Use as a Real-Time Clock ....................................... 132 Timer2 .............................................................................. 135 Associated Registers ............................................... 136 Interrupt .................................................................... 136 Operation ................................................................. 135 Output ...................................................................... 136 PR2 Register .................................................... 146, 151 TMR2 to PR2 Match Interrupt .......................... 146, 151 Timer3 .............................................................................. 137 16-Bit Read/Write Mode ........................................... 139 Associated Registers ............................................... 139 Operation ................................................................. 138 Oscillator .......................................................... 137, 139 Overflow Interrupt ............................................ 137, 139 Special Event Trigger (CCP) .................................... 139 TMR3H Register ...................................................... 137 TMR3L Register ....................................................... 137 Timing Diagrams A/D Conversion ........................................................ 397 Acknowledge Sequence .......................................... 230 Asynchronous Reception (TXCKP = 0, TX Not Inverted) .............................................. 251 Asynchronous Transmission (TXCKP = 0, TX Not Inverted) .............................................. 248 Asynchronous Transmission, Back to Back (TXCKP = 0, TX Not Inverted) ......................... 248 Automatic Baud Rate Calculation ............................ 246 Auto-Wake-up Bit (WUE) During Normal Operation ............................................ 252 Auto-Wake-up Bit (WUE) During Sleep ................... 252 Baud Rate Generator with Clock Arbitration ............ 224 BRG Overflow Sequence ......................................... 246 BRG Reset Due to SDA Arbitration During Start Condition ..................................... 233 Brown-out Reset (BOR) ........................................... 383 Bus Collision During a Repeated Start Condition (Case 1) ........................................... 234 Bus Collision During a Repeated Start Condition (Case 2) ........................................... 234 Bus Collision During a Start Condition (SCL = 0) ......................................... 233 Bus Collision During a Start Condition (SDA only) ....................................... 232 Bus Collision During a Stop Condition (Case 1) ........................................... 235 Bus Collision During a Stop Condition (Case 2) ........................................... 235 Bus Collision for Transmit and Acknowledge ................................................... 231 Capture/Compare/PWM (All CCP Modules) ........................................... 385 CLKO and I/O .......................................................... 382 Clock Synchronization ............................................. 217 Clock/Instruction Cycle .............................................. 61 EUSART Synchronous Receive (Master/Slave) ................................................. 394 EUSART Synchronous Transmission (Master/Slave) ................................................. 394 Example SPI Master Mode (CKE = 0) ..................... 386 Example SPI Master Mode (CKE = 1) ..................... 387 Example SPI Slave Mode (CKE = 0) ....................... 388 Example SPI Slave Mode (CKE = 1) ....................... 389 External Clock (All Modes Except PLL) ................... 380 Fail-Safe Clock Monitor ........................................... 301 First Start Bit Timing ................................................ 225 Full-Bridge PWM Output .......................................... 155 Half-Bridge PWM Output ......................................... 154 High/Low-Voltage Detect Characteristics ................ 377 High-Voltage Detect (VDIRMAG = 1) ...................... 282 I2C Bus Data ............................................................ 390 I2C Bus Start/Stop Bits ............................................ 390 I2C Master Mode (7 or 10-Bit Transmission) ........... 228 I2C Master Mode (7-Bit Reception) ......................... 229 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 213 I2C Slave Mode (10-Bit Reception, SEN = 0, ADMSK 01001) ................................ 214 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 219 I2C Slave Mode (10-Bit Transmission) .................... 215 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 210 I2C Slave Mode (7-bit Reception, SEN = 0, ADMSK = 01011) ............................................ 211 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 218 I2C Slave Mode (7-Bit Transmission) ...................... 212 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ............ 220 Low-Voltage Detect (VDIRMAG = 0) ....................... 281 Master SSP I2C Bus Data ....................................... 392 Master SSP I2C Bus Start/Stop Bits ........................ 392 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 160 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 160 PWM Direction Change ........................................... 157 PWM Direction Change at Near 100% Duty Cycle ............................................. 157 PWM Output ............................................................ 146 Repeated Start Condition ........................................ 226 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ................................................. 383 Send Break Character Sequence ............................ 253 Slave Synchronization ............................................. 199 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 49 SPI Mode (Master Mode) ........................................ 198 SPI Mode (Slave Mode with CKE = 0) ..................... 200 SPI Mode (Slave Mode with CKE = 1) ..................... 200 SPP Write Address and Data for USB (4 Wait States) ................................................. 189 SPP Write Address and Read Data for USB (4 Wait States) ................................................. 189 SPP Write Address, Write and Read Data (No Wait States) .............................................. 189 Stop Condition Receive or Transmit Mode .............. 230 Streaming Parallel Port (PIC18F4455/4550) ........... 396 Synchronous Reception (Master Mode, SREN) ..................................... 256 |
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