PIC18F4550ESOSQTP datasheet(424/430 Pages) MICROCHIP

424 / 430 page

PIC18F2455/2550/4455/4550

DS39632D-page 422

Preliminary

Synchronous Transmission ...................................... 254

Synchronous Transmission (Through TXEN) .......... 255

Time-out Sequence on POR w/PLL Enabled

(MCLR Tied to VDD) ........................................... 49

Time-out Sequence on Power-up

(MCLR Not Tied to VDD), Case 1 ....................... 48

Time-out Sequence on Power-up

(MCLR Not Tied to VDD), Case 2 ....................... 48

Time-out Sequence on Power-up

(MCLR Tied to VDD, VDD Rise TPWRT) .............. 48

Timer0 and Timer1 External Clock .......................... 384

Transition for Entry to Idle Mode ................................ 40

Transition for Entry to SEC_RUN Mode .................... 37

Transition for Entry to Sleep Mode ............................ 39

Transition for Two-Speed Start-up

(INTOSC to HSPLL) ......................................... 299

Transition for Wake from Idle to Run Mode ............... 40

Transition for Wake from Sleep (HSPLL) ................... 39

Transition From RC_RUN Mode to

PRI_RUN Mode ................................................. 38

Transition from SEC_RUN Mode to

PRI_RUN Mode (HSPLL) .................................. 37

Transition to RC_RUN Mode ..................................... 38

USB Signal ............................................................... 395

Timing Diagrams and Specifications ................................ 380

Capture/Compare/PWM Requirements

(All CCP Modules) ........................................... 385

CLKO and I/O Requirements ................................... 382

EUSART Synchronous Receive

Requirements ................................................... 394

EUSART Synchronous Transmission

Requirements ................................................... 394

Example SPI Mode Requirements

(Master Mode, CKE = 0) .................................. 386

Example SPI Mode Requirements

(Master Mode, CKE = 1) .................................. 387

Example SPI Mode Requirements

(Slave Mode, CKE = 0) .................................... 388

Example SPI Mode Requirements

(Slave Mode, CKE = 1) .................................... 389

External Clock Requirements .................................. 380

I2C Bus Data Requirements (Slave Mode) .............. 391

I2C Bus Start/Stop Bits Requirements ..................... 390

Master SSP I2C Bus Data Requirements ................ 393

Master SSP I2C Bus Start/Stop Bits

Requirements ................................................... 392

PLL Clock ................................................................. 381

Reset, Watchdog Timer, Oscillator Start-up

Timer, Power-up Timer and Brown-out

Reset Requirements ........................................ 383

Streaming Parallel Port Requirements

(PIC18F4455/4550) ......................................... 396

Timer0 and Timer1 External Clock

Requirements ................................................... 384

USB Full-Speed Requirements ................................ 395

USB Low-Speed Requirements ............................... 395

Top-of-Stack Access .......................................................... 58

TQFP Packages and Special Features ............................ 305

TSTFSZ ............................................................................ 347

Two-Speed Start-up ................................................. 285, 299

Two-Word Instructions

Example Cases .......................................................... 62

TXSTA Register

BRGH Bit ................................................................. 241

Universal Serial Bus .......................................................... 63

Address Register (UADDR) ..................................... 170

and Streaming Parallel Port ..................................... 183

Associated Registers ............................................... 184

Buffer Descriptor Table ............................................ 171

Buffer Descriptors .................................................... 171

Address Validation ........................................... 174

Assignment in Different

Buffering Modes ...................................... 176

BDnSTAT Register (CPU Mode) ..................... 172

BDnSTAT Register (SIE Mode) ....................... 174

Byte Count ....................................................... 174

Example ........................................................... 171

Memory Map .................................................... 175

Ownership ....................................................... 171

Ping-Pong Buffering ........................................ 175

Status and Configuration ................................. 171

Class Specifications and Drivers ............................. 186

Descriptors ............................................................... 186

Endpoint Control ...................................................... 169

Enumeration ............................................................ 186

External Pull-up Resistors ....................................... 167

External Transceiver ................................................ 165

Eye Pattern Test Enable .......................................... 167

Firmware and Drivers .............................................. 184

Frame Number Registers ........................................ 170

Frames .................................................................... 185

Internal Pull-up Resistors ......................................... 167

Internal Transceiver ................................................. 165

Internal Voltage Regulator ....................................... 167

Interrupts ................................................................. 177

and USB Transactions ..................................... 177

Layered Framework ................................................. 185

Oscillator Requirements .......................................... 184

Output Enable Monitor ............................................. 167

Overview .......................................................... 163, 185

Ping-Pong Buffer Configuration ............................... 167

Power ...................................................................... 185

Power Modes ........................................................... 183

Bus Power Only ............................................... 183

Dual Power with Self-Power

Dominance .............................................. 183

Self-Power Only ............................................... 183

RAM ......................................................................... 170

Memory Map .................................................... 170

Speed ...................................................................... 186

Status and Control ................................................... 164

Transfer Types ......................................................... 185

UFRMH:UFRML Registers ...................................... 170

USB. See Universal Serial Bus.

PIC18F4550ESOSQTP Datasheet(PDF) 424 Page - Microchip Technology

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