MSC1202Y2RHHT datasheet(24/92 Pages) TI1

24 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

www.ti.com

ADC ANALOG INPUT

When the buffer is not selected, the input impedance of the

analog input changes with ACLK clock frequency (ACLK,

SFR F6h) and gain (PGA). The relationship is:

Impedance (

W) +

SAMP @ CS

IN Impedance (W) +

1MHz

ACLK Frequency

@ 7MW

PGA

where ACLK frequency (f

ACLK) +

CLK

ACLK

) 1

and f

MOD +

ACLK

NOTE: The input impedance for PGA = 128 is the same as

that for PGA = 64 (that is, 7M

Ω/64).

Figure 9 shows the basic input structure of the MSC120x.

SWITCH

(3k

Ωtypical)

Sampling Frequency = f

SAMP

High Impedance

>1G

Ω

AGND

PGA

SAMP

1, 2, 4

MOD

× f

MOD

× f

MOD

× f

MOD

64, 128

× f

MOD

PGA

9pF

18pF

4 to 128

36pF

MOD =

ACLK

Figure 9. Analog Input Structure (without Buffer)

ADC PGA

The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.

Using the PGA can actually improve the effective

resolution of the ADC. For instance, with a PGA of 1 on a

±2.5V full-scale range (FSR), the ADC can resolve to

1.5

µV. With a PGA of 128 on a ±19mV FSR, the ADC can

resolve to 75nV. With a PGA of 1 on a

±2.5V FSR, it would

require a 26-bit ADC to resolve 75nV, as shown in Table 1.

Table 1. ENOB versus PGA (Bipolar Mode)

FULL-

MSC1200

MSC1201

MSC1202

ENOB(1)

RMS

INPUT-REFERRED

NOISE

PGA

SETTING

FULL-

SCALE

RANGE

(V)

MSC1201

ENOB(1)

AT 10HZ

(BITS)

ENOB(1)

UP TO

200HZ

(BITS)

MSC1200

MSC1201

(nV)

MSC1202

(

mV)

±2.5

21.7

1468

76.3

±1.25

21.5

15.6

843

38.1

±0.625

21.4

15.5

452

19.1

±0.313

21.2

15.4

259

9.5

±0.156

20.8

15.4

171

4.8

±0.078

20.4

15.3

113

2.4

±0.039

15.2

74.5

128

±0.019

14.2

74.5

0.6

(1) ENOB = Log2(FSR/RMS Noise) = Log2(224) − Log2(σCODES)

= 24 − Log2(σCODES)

ADC OFFSET DAC

The analog output from the PGA can be offset by up to half

the full-scale range of the ADC by using the ODAC register

(SFR E6h). The ODAC (Offset DAC) register is an 8-bit

value; the MSB is the sign and the seven LSBs provide the

magnitude of the offset.

ADC MODULATOR

The modulator is a single-loop, 2nd-order system. The

modulator runs at a clock speed (fMOD) that is derived from

CLK using the value in the Analog Clock register (ACLK,

SFR F6h). The data output rate is:

Data Rate

+ f

DATA

MOD

Decimation Ratio

where f

MOD +

CLK

(ACLK

) 1) @ 64

ACLK

and Decimation Ratio is set in [ADCON3:ADCON2]

ADC CALIBRATION

The offset and gain errors in the MSC120x, or the complete

system, can be reduced with calibration. Calibration is

controlled through the ADCON1 register (SFR DDh), bits

CAL2:CAL0. Each calibration process takes seven tDATA

periods (data conversion time) to complete. Therefore, it

takes 14 tDATA periods to complete both an offset and gain

calibration.

MSC1202Y2RHHT Datasheet(PDF) 24 Page - Texas Instruments

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