AS3517H-ECTP datasheet(86/94 Pages) AMSCO

86 / 94 page

AS3517 V17

Data Sheet, Confidential

www.austriamicrosystems.com

Name

Base

Default

IRQ_ENRD_2

2-wire serial

00h

Third Interrupt Register

Offset: 25h

Please be aware that writing to this register will enable/disable the corresponding

interrupts, while with reading you get the actual interrupt status and will clear the

settings. This register is reset at a DVDD-POR.

Bit

Bit Name

Default

Access

Bit Description

Real time clock supply (RVDD) under-voltage interrupt setting

0: disable

1: enable

RVDD_LOW

(level)

Real time clock supply interrupt reading

0: RTC supply o.k.

1: RTC supply (RVDD) was low, RTC not longer valid

The interrupt gets set in hibernation or during power-up even if

the interrupt is not enabled thus allowing to recognise a

change of the battery connected to BVDDR during hibernation

or shutdown. For a valid reading, the interrupt has to be

enabled first.

BVDD under-voltage supervisor interrupt setting

0: disable

1: enable

BVDD_LOW

(level)

BVDD supervisor interrupt setting

0: BVDD is above brown out level

1: BVDD has reached brown out level

The threshold can be set in the SUPERVISOR register (24h)

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