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AS3517H-ECTP Datasheet(PDF) 57 Page - ams AG |
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AS3517H-ECTP Datasheet(HTML) 57 Page - ams AG |
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57 / 94 page  AS3517 V17 Data Sheet, Confidential © 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Addr Name D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> - MUTE_OFF _A - ADL_VOL Gain from MUX_A to ADC (N18) = (-34.5dB … +12dB) 11h ADC_L 0 0 0 0 0 0 0 0 DRIVE_PWGD 0: 12mA OD; 1: 12mA PP 2: 4mA PP; 3: 2mA PP MUX_PWGD 0: PWGD; 1: PWM 2: SPDIF; 3: PLL clock DRIVE_Q32K 0: 12mA PP; 1: 12mA OD 2: 4mA PP; 3: 2mA PP MUX_Q32K 0: Q32K; 1: PWM 2: SPDIF; 3: PLL clock 12h-1 OutContr1 0 0 0 0 0 0 0 0 DRIVE_Q24M 0: 12mA PP; 1: 12mA OD 2: 4mA PP; 3: 2mA PP MUX_Q24M 0: Q24 1: PLL clock SPDIF_ COPY_OK SPDIF_ MCLK_INV SPDIF_ INVALID SPDIF_CNTR 0: OFF; 1: 32kS 2: 44.1kS; 3: 48kS 12h-2 OutContr2_SP DIF 0 0 0 0 0 0 0 0 PWM_ INVERTED PWM_CYCLE 0: no pulses; DytyCycle = PWM_CYCLE * 0.3937% 12h-3 PWM 0 0 0 0 0 0 0 0 ADC_R_ON ADC_L_ON LOUT2_ON LOUT1_ON LIN2_ON LIN1_ON MIC2_ON MIC1_ON 14h AudioSet_1 0 0 0 0 0 0 0 0 BIAS_OFF SUM_OFF AGC_OFF IBR_DAC DAC_ON - 15h AudioSet_2 0 0 0 0 0 0 0 0 LIN1MIX_O FF LIN2MIX_O FF MIC1MIX_O FF MIC2MIX_O FF DACMIX_O FF ZCU_OFF IBR_HPH HPCM_ON 16h AudioSet_3 0 0 0 0 0 0 0 0 LDO_PVDD 1_OFF - PROG_ PVDD1 VSEL_PVDD1 0h – Fh:1.2V+VSEL*50mV (1.2V – 1.95V) 10h – 1Fh: 2.0V+(VSEL-10h)*100mV (2.0V – 3.5V) 17h-1 PMU PVDD1 0 0 0 0 0 0 0 0 LDO_PVDD 2_OFF - PROG_ PVDD2 VSEL_PVDD2 0h – Fh:1.2V+VSEL*50mV (1.2V – 1.95V) 10h – 1Fh: 2.0V+(VSEL-10h)*100mV (2.0V – 3.5V) 17h-2 PMU PVDD2 0 0 0 0 0 0 0 0 SKIP_OFF_ CVDD1 PROG_ CVDD1 VSEL_CVDD1 0h: OFF; 1h - 38h …. 0.6V+VSEL*50mV 0.65V – 3.40V; (38h – 3Fh …. 3.4V) 17h-3 PMU CVDD1 0 0 0 0 0 0 0 0 SKIP_OFF_ CVDD2 PROG_ CVDD2 VSEL_CVDD2 0h: OFF; 1h - 38h …. 0.6V+VSEL*50mV 0.65V – 3.40V; (38h – 3Fh …. 3.4V) 17h-4 PMU CVDD2 0 0 0 0 0 0 0 0 SKIP_OFF_ CVDD3 PROG_ CVDD3 VSEL_CVDD3 0h: OFF; 1h - 38h …. 0.6V+VSEL*50mV 0.65V – 3.40V; (38h – 3Fh …. 3.4V) 17h-5 PMU CVDD3 0 0 0 0 0 0 0 0 - KEEP_ PVDD2 KEEP_ PVDD1 KEEP_ VLED KEEP_ VBUS KEEP_ CVDD3 KEEP_ CVDD2 KEEP_ CVDD1 17h-6 PMU Hibernate 0 0 0 0 0 0 0 0 - DC_TEST 0: unused; 1: AVDD; 2: DVDD; 3: PVDD1 4: PVDD2; 5: CVDD1; 6; CVDD2; 7: CVDD3 PMU_GATE PMU_WR_ENABLE 1: prog 17h-1 / 12h-1 (PVDD1, OutContr1) 2: prog 17h-2 / 12h-2 (PVDD2, OutContr2) 3: prog 17h-3 / 12h-3 (CVDD1, PWM) 4: prog 17h-4 (CVDD2); 5: prog 17h-5 (CVDD3) 6: prog 17h-6 (Hibernate); 0,7: unused 18h PMU Enable 0 0 0 0 0 0 0 0 1st write/read: WAKEUP_BYTE_1 128s 64s 32s 16s 8s 4s 2s 1s 2nd write/read: WAKEUP_BYTE_2 32ks 16ks 8ks 4ks 2ks 1ks 512s 256s 3rd wirte/read: WAKEUP_BYTE_3 EnableWakeup 4k*1ks 2k*1ks 1k*1Ks 512ks 256ks 128ks 64ks 19h RTC_WakeUp 4th to 19th write/read: SRAM_128 I_PMOS_GATE 0: 1µA; 1: 2µA 2: 3µA; 3: 4µA DCDC_PS_ OFF DCDC_ PMOS_OFF VBUS_COMP_TH 0: 4.5V; 1: 3.18V 2: 1.5V; 3: 0.6V VBUS_SKIP _ON VBUS_ON 1Ah USB_UTIL_DC DC 0 0 0 0 0 0 0 0 DIM_UP_D OWN DIM_RATE 0: no dimming; 1: 150ms 2: 300ms; 3: 500ms I_BACKLIGHT 0 … OFF 1-31 … LED current = 1.25mA*I_BACKLIGHT (1.25mA … 38.75mA) 1Bh DCDC15 0 0 0 0 0 0 0 0 Revision 1v3 56 - 93 |
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