AS3658F-BCTP datasheet(125/158 Pages) AMSCO

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AS3658

Data Sheet Confidential - Deta il ed Descri ption - System Functi ons

10.3

Interrupt Controller

The interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the

Interrupt 1…3 register is set by pulling low pin XINT. All the interrupt sources can be enabled in the Interrupt Mask 1…3

AS3658 device from losing an interrupt event, the register that is read is captured before it is transmitted to the host

controller via the serial interface. As soon as the transmission of the captured value is complete a logical AND

operation with the bit wise inverted captured value is applied to the register to clear all interrupt bits that have already

been transmitted. Clearing the read interrupt bits takes 2 clock cycles, a read access to the same register before the

clearing process has completed will yield a value of ‘0’. Note that an interrupt that has been present at the previous

read access will be cleared as well in case it occurs again before the clearing process has completed.

During a read access to one of the interrupt registers the XINT pin will be released. As soon as the transferred bits of

the interrupt register have been cleared the XINT pin will be pulled low in case a new interrupt has occurred in the

meantime. By doing so the interrupt controller will work correctly with host controllers that are edge- and level-sensitive

on their interrupt request input. Multiple byte read access is recommended to avoid reading the Interrupt 1 register

over and over again in response to a new interrupt that has occurred in the same register (and thus pulling low pin

XINT) before the Interrupt 2,3 register has been read.

Table 131. Interrupt Status 1 Register

Addr:50

Interrupt Status1

These bits show the status of the interrupts

Bit

Bit Name

Default

Access

Description

chstate_i

Bit is set when the following status bits are set or reset:

Trickle, CVM, NoBat

cheoc_i

Bit is set when the EOC status bits are set or reset:

charging_tmax_i

Bit is set when charge timeout ( tricke, CV, CC) has

been expired

usb_chdet_i

Bit is set when the USB_ChDet Bit is set or reset.

chdet_i

Bit is set when the ChDet Bit is set or reset.

Onkey_i

Bit is set when status XON bit is set or reset.

ovtmp_i

Bit is set when the lower temperature threshold

Temp110 of the temperature sensor is exceeded for

longer than tRESMASK.

Lowsup

Bit is set when the main supply voltage VSUPPLY has

dropped below VRESFALL for longer than tRESMASK.

Table 132. Interrupt Status 2 Register

Addr:51

Interrupt Status2

These bits show the status of the interrupts

Bit

Bit Name

Default

Access

Description

sd1_lv_i

Bit is set when voltage of step down1 drops below low

voltage threshold (1msec debounce timer)

sd2_lv_i

Bit is set when voltage of step down2 drops below low

voltage threshold

(1msec debounce timer)

sd3_lv_i

Bit is set when voltage of step down3 drops below low

voltage threshold

(1msec debounce timer)

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