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AS3658F-BCTP Datasheet(PDF) 122 Page - ams AG |
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AS3658F-BCTP Datasheet(HTML) 122 Page - ams AG |
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122 / 158 page ![]() www.austriamicrosystems.com Revision 1v13 121 - 157 AS3658 Data Sheet Confidential - Deta il ed Descri ption - System Functi ons 6:3 reset_reason NA R Flags to indicate to the software the reason for the last reset 0000 VPOR has been reached (battery or charger insertion from scratch) 0001 VRESETFALLING was reached (battery voltage drop below 2.75V) 0010 software forced by force_reset 0011 software forced by power_off and XON was pulled low 0100 software forced by power_off and charger was detected 0101 external triggered through the pin RESET 0110 reset caused by overtemperature T140 0111 reset caused by watchdog 1000 reset caused by 5 seconds on press 1001 reset caused by rtc_alarm register 1010 reset caused by rtc repeated wakeup 1011 reset caused by interrupt in standby mode 1100 reset caused by XON pulled low in standby mode 7 Onkey_reset_5s 1 R/W 0 Reset after 5 seconds ON pressed disabled 1 Reset after 5 seconds ON pressed enabled Table 127. Internal references Bit definitions Addr:59 Internal references Bit definitions These bits control the internal reference mode and internal clk frequency Bit Bit Name Default Access Description 4 standby_mode_on 0 W Setting to ‘1’ sets the AS3658 into standby mode. All regulators defined in reg.17h “Reg Power1Ctrl” and reg.1Eh “Reg Power2 Ctrl are disabled except those regulators enabled by reg.81h “Reg standby mode”. XRESET will be pulled to low. A normal startup of all regulators will be done with any interrupt (has to be enabled before entering standby mode). During this startup, regulators defined by Reg standby mode register are continuously on. 5 Clk_div2 0 R/W Divide internal clock oscillator by 2 to reduce quiescent current for low power operation 0 Normal mode 1 Internal clock frequency divided by two. All timings are increased by two. Switching frequency of all DCDC converters are divided by two. Reduced transient performance of DCDC converters. Table 126. Reset Control Register Addr:105 Reset Control These bits control the power off mode and reset timer Bit Bit Name Default Access Description |
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