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AS3658F-BCTP Datasheet(PDF) 119 Page - ams AG |
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AS3658F-BCTP Datasheet(HTML) 119 Page - ams AG |
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119 / 158 page ![]() www.austriamicrosystems.com Revision 1v13 118 - 157 AS3658 Data Sheet Confidential - Deta il ed Descri ption - System Functi ons Figure 55. I 2 C Current-Address-Read: To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random-Read, a single byte transfer is terminated with a not-acknowledge after the 1 st register byte. Analogous to Sequential-Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not- acknowledge following the last data byte and a subsequent STOP condition. 10.2 Reset generator and XON-Key XRESET is a low active bi-directional pin. An external pull-up to the periphery supply has to be added. During each reset cycle the following states are controlled by the AS3658: Pin XRESET is forced to GND Programmable Power-off function Programmable Power-on sequence and regulator voltages Programmable reset timer All registers are set to their default values after power-on, except the reset control- and status-registers. Note: Programming is controlled by the internal Mask-PROM and the external resistor RPROGRAM Table 123. XRESET,XON Characteristics Symbol Parameter Min Typ Max Unit Note 10.2.1 Reset Conditions Reset can be activated from 7 different sources: Power on (battery or charger insertion) Low Battery Software forced reset Power off mode External triggered through the pin RESET Overtemperature Watchdog VXRESET_IL XRESET Low Level input voltage -0.3 0.4 V VXRESET_IH XRESET High Level input voltage 1.3 VSUPP LY V VXON_IL XON Low Level input voltage -0.3 0.3*V2 _5 VXON_IH XON High Level input 0.7*V2 _5 V2_5 IXON_PUP XON Pull up current 12 µA A data 1 read register WA++ S DR data 2 A read register WA++ N P WA++ … data n A read register WA++ |
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