CS5317 datasheet(12/32 Pages) CIRRUS

12 / 32 page

ioutavg = Kd(θ1−θ2) ≈ (−50µA ⁄ 2π) (θ1−θ2)

where

θ1 is the phase of IN1, θ2 is the phase of

IN2 and Kd is the phase detector gain. The factor

π comes from averaging the current over a full

CLKIN cycle.

Kd is in units of micro-am-

peres/radian

VCO Gain (Ko)

The output frequency from the VCO ranges from

1.28 MHz to 5.12 MHz. The frequency is a func-

tion of the control voltage input to the VCO. The

VCO has a negative gain factor, meaning that as

the control voltage increases more positively the

output frequency decreases. The gain factor units

are Megaradians per Volt per Second.

This is

equivalent to 2

π Megahertz per volt. Changes in

output frequency are given by:

∆ωvco = Ko ∆VCOin [Ko is typ. -10Mrad/Vs.]

Counter/Divider Ratio

The CS5317 PLL multiplies the CLKIN rate by

an integer value. To set the multiplication rate, a

counter/divider chain is used to divide the VCO

output frequency to develop a clock whose fre-

quency is compared to the CLKIN frequency in

the phase detector. The binary counter/divider ra-

tio sets the ratio of the VCO frequency to the

CLKIN frequency. As illustrated in Figure 5, the

VCO output is always divided by two to yield the

CLKOUT signal which is identical in frequency

to the delta-sigma modulator sampling clock.

The CLKOUT signal is then further divided by

either 128 in the CLKG1 mode or by 256 in the

CLKG2 mode. When the divide by two stage is

included, the divider ratio (N) for the PLL in the

CLKG1 mode is effectively 256. In the CLKG2

mode the divider ratio (N) is 512.

Loop Transfer Function

As the phase-locked loop is a closed loop system,

an equation can be determined which describes its

closed loop response. Using the gain factors for

the phase detector and the VCO, the filter ar-

rangement and the counter/divider constant N,

analysis will yield the following equation which

describes the transfer function of the PLL:

θ2

θ1

KoKdR

KoKd

2 + KoKdR

KoKd

This equation may be rewritten such that its ele-

ments

correspond

with

the

following

Phase/Frequency

Detect Logic

IN1

IN2

DOWN

CLKIN

+5V

-5V

VA+

VCO

128

Conversion Output Rate -

Same Frequency as DOUT

Internal Sync for Digital Filter

Delta-Sigma

Sampling Clock

CLKG1

CLKG2

CLKOR

VCOIN

External RC

Kd = -8 µA/rad

K0 = -10 Mrad/V.s

µA

(CLKOUT)

PHDT

Figure 5. PLL Functional Diagram

CS5317

DS27F4

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