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CS5317 Datasheet(PDF) 13 Page - Cirrus Logic

Part # CS5317
Description  16-Bit, 20 kHz Oversampling A/D Converter
PDF  32 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5317 Datasheet(HTML) 13 Page - Cirrus Logic

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characteristic form in which the damping factor,
ζ, and the natural frequency, ωn , are evident:
θ2
θ1
=
2
ζωns + ωn 2
s
2 + 2ζωns + ωn 2
Both the natur al frequency and the damping fac-
tor are particularly important in determining the
transient response of the phase-locked loop when
subjected to a step input of phase or frequency. A
family of curves are illustrated in Figure 6 that
indicate the overshoot and stability of the loop as
a function of the damping factor. Each response is
plotted as a function of the normalized time,
ωn t.
For a given
ζ and lock time, t, the ωn required
can be determined. Alternatively, phase lock con-
trol loop bandwidth may be a specified parameter.
In some systems it may be desirable to reduce the
-3dB bandwidth of the PLL control loop to re-
duce the effects of jitter in the phase of the input
clock. The 3 dB bandwidth of the PLL control
loop is defined by the following equation:
ω3dB = ωn
√
2
ζ2 + 1 +

(2ζ2 + 1)2 + 1
The equations used to describe the PLL and the
3 dB bandwidth are valid only if the frequency of
CLKIN is approximately 20 times greater than
the 3 dB corner frequency of the control loop.
Filter Components
Using the equations which describe the transfer
function of the PLL system, the following exter-
nal filter component equations can be determined:
C
=
KoKd
N
ωn 2
R
= 2
ζωn
N
KoKd
The gain factors (Ko, Kd) are specified in the
Analog Characteristics table. In the event the sys-
tem calls for very low bandwidth, hence a
corresponding reduction in loop gain, the phase
detector gain factor Kd can be reduced. A large
series resistor (R1) can be inserted between the
output of the detector and the filter. Then the
50
µA current sources will saturate to the supplies
and yield the following gain factor:
Kd
−5V
2
πR1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
01
23
456
78
9
10
0.1
1
10
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
Figure 6a.
θ2 Unit Step Response
Figure 6b. Second Order PLL Frequency Response
ω
n
t.
θ
2
normalized to
θ
1
ω/ω
n
20 log(
θ
2
/
θ
1
)
ζ = 0.5
ζ = 0.6
ζ = 0.7
ζ = 0.8
ζ = 0.9
ζ = 1.0
ζ = 1.5
ζ = 2.0
ζ = 3.0
ζ = 10.0
ζ= 10.0
ζ= 0.5
ζ = 0.5
ζ = 10
CS5317
DS27F4
13



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