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CS5317 Datasheet(PDF) 27 Page - Cirrus Logic |
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CS5317 Datasheet(HTML) 27 Page - Cirrus Logic |
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27 / 32 page ![]() amplitude so that distortion products become neg- ligible. This allows an accurate measurement of the noise floor. More complex analysis such as intermodulation distortion measurements can be accomplished with the addition of another sine-wave generator. CIRCUIT DESCRIPTION Figure 2 illustrates the CS5317 A/D converter IC circuit connections. The chip operates off of ±5V. These voltages are supplied from a power source external to the evaluation board. Binding posts are supplied on the board to connect the +5, -5, and ground power lines. A good quality low rip- p le, low no ise su pp ly will giv e the best performance. The +5 V supply can also be used for VL and should be connected between the VL board jack and the power supply, as opposed to connecting the VL jack straight to the +5V jack. The +5V jack is the positive power source for the CS5317 IC whereas the VL jack supplies power to all the digital ICs. Care should be taken that noise is not coupled between VL and +5V; how- ever, supply noise is generally not a problem with the CS5317 since the on-chip decimation filter will remove any interference outside of its pass- band. The +5 and -5 V supply lines are filtered on U6 9 11 CLKIN GND -5V AIN TP10 17 18 R11 15 12 R8 10 C13 C12 CLKG1 CLKG2 CLKOR CLKIN (fig.6) P2 10 µF TP9 C18 C16 10 µF D2 6.8v TP7 + TP8 R1* R2 200 51 10k CS5317 +5V D3 C19 C17 R10 6.8v 0.22 µF R7 10 VA+ 1 VD+ 2 C7 0.1 µF C6 10 µF R5 10 k CLKOUT DATA DOUT (fig. 3) (fig. 3) (fig. 3) R9 10 k R6 10 k 7 16 4 3 5 6 8 0.1 µF C15 0.1 µF 0.1 µF C14 TP6 D1 C4 C5 0.1 µF VL VL 10 µF VA- 14 VD- 10 C8 0.1 µF C9 10 µF * Remove for logic gate CLKIN source DGND CLKOUT DATA MODE RST DOE DOUT AIN CLKIN AGND REFBUF PHDT VCOIN + 1.2k 0.01 µF NPO Figure 2. Analog-to-Digital Converter CDB5317 DS27DB3 27 |
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