AT45DB021D_13 datasheet(33/48 Pages) ETC2

33 / 48 page

3638M–DFLASH–5/2013

AT45DB021D

Figure 17-3. Waveform 3 – RapidS Mode 0 (FMAX = 66MHz)

Figure 17-4. Waveform 4 – RapidS Mode 3 (FMAX = 66MHz)

17.1 Utilizing the RapidS Function

To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be

used to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out

on the falling edge of the SCK signal and clock data in on the rising edge of SCK.

For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the falling edge of SCK,

the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller

should clock its data out on the rising edge of SCK in order to give the DataFlash a full clock cycle to latch the

incoming data in on the next rising edge of SCK.

SCK

tCSS

VALID IN

tSU

tWH

tWL

tCSH

tCS

HIGH IMPEDANCE

VALID OUT

tHO

tDIS

HIGH IMPEDANCE

SCK

tCSS

VALID IN

tSU

tWL

tWH

tCSH

tCS

HIGH Z

VALID OUT

tHO

tDIS

HIGH IMPEDANCE

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