AT45DB021D_13 datasheet(34/48 Pages) ETC2

34 / 48 page

3638M–DFLASH–5/2013

AT45DB021D

Figure 17-5. RapidS Mode

Figure 17-6. Reset Timing

Note:

The CS signal should be in the high state before the RESET signal is deasserted

Figure 17-7. Command Sequence for Read/Write Operations for Page Size 256-Bytes (Except Status Register

Read, Manufacturer and Device ID Read)

SCK

MOSI

MISO

MOSI = Master Out, Slave In

MISO = Master In, Slave Out

The Master is the host controller and the Slave is the DataFlash

The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.

The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.

Master clocks out first bit of BYTE-MOSI on the rising edge of SCK

Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK

Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK

Last bit of BYTE-MOSI is clocked out from the Master

Last bit of BYTE-MOSI is clocked into the slave

Slave clocks out first bit of BYTE-SO

Master clocks in first bit of BYTE-SO

Slave clocks out second bit of BYTE-SO

Master clocks in last bit of BYTE-SO

BYTE-MOSI

MSB

LSB

BYTE-SO

MSB

LSB

Slave

SCK

RESET

SO (OUTPUT)

HIGH IMPEDANCE

SI (INPUT)

tRST

tREC

tCSS

SI (INPUT)

CMD

8 bits

Page Address

(A17 - A8)

X X X X X X

X X

X X X X X X X X

LSB

X X X X X X X X

Byte/Buffer Address

(A7 - A0/BFA7 - BFA0)

MSB

6 Don’t Care

Bits

AT45DB021D Datasheet(PDF) 34 Page - List of Unclassifed Manufacturers

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