AN2352

Configuration of the CAN bit timing

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Figure 3.

Synchronization on “late” and “early” edges

In the first example, an edge from recessive to dominant occurs at the end of Prop_Seg.

The edge is “late” since it occurs after the Sync_Seg. Reacting to the “late” edge,

Phase_Seg1 is lengthened so that the distance from the edge to the sample point is the

same as it would have been from the Sync_Seg to the sample point if no edge had

occurred. The phase error of this “late” edge is less than the SJW, so it is fully compensated

and the edge from dominant to recessive at the end of the bit, which is one nominal bit time

long, occurs in the Sync_Seg.

In the second example, an edge from recessive to dominant occurs during Phase_Seg2.

The edge is “early” since it occurs before a Sync_Seg. Reacting to the “early” edge,

Phase_Seg2 is shortened and Sync_Seg is omitted, so that the distance from the edge to

the sample point is the same as it would have been from an Sync_Seg to the sample point if

no edge had occurred. As in the previous example, the magnitude of this “early” edge’s

phase error is less than the SJW, so it is fully compensated.

The phase buffer segments are lengthened or shortened only temporarily; at the next bit

time, the segments return to their nominal programmed values.

In these examples, the bit timing is seen from the point of view of the CAN implementation’s

state machine, where the bit time starts and ends at the sample points. The state machine

omits Sync_Seg when synchronizing on an “early” edge because it cannot subsequently

redefine that time quantum of Phase_Seg2 where the edge occurs to be the Sync_Seg.

recessive

dominant

recessive

dominant

Sync_Seg

Prop_Seg

Phase_Seg1

Phase_Seg2

“late” edge

“early” edge

Rx-input

Rx-input

Sample-point

Sample-point

Sample-point

Sample-point

Sample-Point

Sample-Point