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AN2352 Datasheet(PDF) 3 Page - STMicroelectronics

Part # AN2352
Description  PLL jitter effects on C-CAN modules of the ST10F27x
PDF  20 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2352 Datasheet(HTML) 3 Page - STMicroelectronics

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AN2352
Configuration of the CAN bit timing
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1
Configuration of the CAN bit timing
Even if minor errors in the configuration of the CAN bit timing do not result in immediate
failure, the performance of a CAN network can be reduced significantly.
In many cases, the CAN bit synchronization compensates a faulty configuration of the CAN
bit timing to such a degree that an error frame is generated only occasionally. In the case of
arbitration however, when two or more CAN nodes simultaneously try to transmit a frame, a
misplaced sample point may cause one of the transmitters to become error passive.
The analysis of such sporadic errors requires a detailed knowledge of the CAN bit
synchronization inside a CAN node and of the CAN nodes’ interaction on the CAN bus.
1.1
Bit time and bit rate
CAN supports bit rates in the range of less than 1 Kbit/s up to 1000 Kbit/s. Each member of
the CAN network has its own clock generator, usually a quartz oscillator. The timing
parameter of the bit time (that is, the reciprocal of the bit rate) can be configured individually
for each CAN node, creating a common bit rate even though the CAN nodes’ oscillator
periods (fosc) may be different.
The frequencies of these oscillators are not absolutely stable. Small variations are caused
by changes in temperature or voltage and by deteriorating components. As long as the
variations remain within a specific oscillator tolerance range (df), the CAN nodes can
compensate the different bit rates by resynchronizing to the bit stream.
According to the CAN specifications, the bit time is divided into four segments (
Figure 1):
●
Synchronization segment
●
Propagation time segment
●
Phase buffer segment 1
●
Phase buffer segment 2
Each segment consists of a specific, programmable number of time quanta (see
Table 1).
The length of the time quantum (tq),which is the basic time unit of the bit time, is defined by
the CAN controller’s system clock fsys and the Baud Rate Prescaler (BRP):
tq = BRP / fsys
The C-CAN’s system clock fsys is the fCPU or fCPU / 2 according to bit 2 of the XMSIC
register.
The synchronization segment (Sync_Seg) is that part of the bit time where edges of the
CAN bus level are expected to occur; the distance between the Sync_Seg and an edge that
occurs outside of Sync_Seg is called the phase error of that edge. The propagation time
segment (Prop_Seg) is intended to compensate the physical delay times within the CAN
network. The phase buffer segments (Phase_Seg1 and Phase_Seg2) surround the sample
point. The (Re)synchronization jump width (SJW) defines how far a resynchronization may
move the sample point within the limits defined by the phase buffer segments to
compensate edge phase errors.



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