DocID025336 Rev 1

5/23

AN4370

BEMF Zero crossing detection internal peripheral

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BEMF Zero crossing detection internal peripheral

Designed to achieve the six step driving mode, the BEMFIP is based on a 6 step counter

(BEMFCNT bits) which selects, according to Figure 2, the floating phase sent to the input of

three comparators in order to detect its BEMF Z crossing event. Of course we will select just

one of the 3 comparator outputs through the BEMFMOD bit and sample it. The PWM

sampling signal will be the one of the input channel (either ILx or IHx) chosen by the

combinations of the following bits: BEMFCNT, BEMFSW, BEMFMOD & BEMFPOL (the

sampling signal could be the driving PMW at the HSides, or the driving PWM at the LSides,

or the active freewheeling PWM at the LSides, or the active freewheeling PWM at the

HSides), whereas the PMW sampling edge will depend upon the combinations of the

BEMFMOD & BEMFPOL bits. Even though everything seems a bit tricky, almost everything

is done automatically by the BEMF IP state machine itself.

Figure 1. BEMFIP block diagram

For instance, according to Figure 2, for BEMCNT = 1 the floating phase sent to the

comparators will always be phase #3, namely the motor terminal connected to SH3 pin, and

the PWM sampling signal will be either IH1 or IL1. With the PWM on the HS MOSFETs

(BEMFSW = 0) and BEMFMOD = 1, selecting the BUS/2 comparator output, the PMW input

signal used to sample the output of the BUS/2 comparator will be IH1, whereas with the

PWM on the LS MOSFETs (BEMFSW = 1) and BEMFMOD = 1, the PMW input signal used

to sample the output of the BUS/2 comparator (BEMFMOD = 1) will be, this time, IL1.