AN3142 datasheet(25/44 Pages) STMICROELECTRONICS

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AN3142

Designing a fixed-off-time PFC

Doc ID 17005 Rev 3

25/44

Supposing there is a 60 µA current flowing into the multiplier divider the lower resistor value

can be calculated as:

Equation 50

A commercial value of 51 k

Ω for the lower resistor is selected. The upper resistor value can

now be calculated:

Equation 51

In this application example a RmultH = 6.6 M

Ω and a RmultL = 51 kΩ have been selected.

Please note that for RmultH a resistor with a suitable voltage rating (>400 V) is needed, or

more resistors in series have to be used.

The voltage on the multiplier pin with the selected component values re-calculated at

minimum line voltage is 1.1 V and at maximum line voltage is 2.99 V. Therefore the multiplier

works correctly within its linear region.

Pin 5 (voltage feed forward): The power stage gain of PFC preregulators varies with the

square of the RMS input voltage. So does the crossover frequency fc of the overall open-

loop gain because the gain has a single pole characteristic. This leads to large trade-offs in

the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 VAC

means having fc 4 Hz @ 88 VAC, resulting in sluggish control dynamics. Additionally, the

slow control loop causes large transient current flow during rapid line or load changes that

are limited by the dynamics of the multiplier output. This limit is considered when selecting

the sense resistor to let the full load power pass under minimum line voltage conditions, with

some margin. But a fixed current limit allows excessive power input at high line, whereas a

fixed power limit requires the current limit to vary inversely with the line voltage. Voltage

feedforward can compensate for the gain variation with the line voltage and allow the

overcoming of all the above-mentioned issues. It consists of deriving a voltage proportional

to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector)

and providing the resulting signal to the multiplier that generates the current reference for

the inner current control loop (

Figure 16). In this way a change of the line voltage causes an

inversely proportional change of the half-sine amplitude at the output of the multiplier (if the

line voltage doubles the amplitude of the multiplier, output is halved and vice versa) so that

the current reference is adapted to the new operating conditions with, ideally, no need to

invoke the slow dynamics of the error amplifier. Additionally, the loop gain is constant

throughout the input voltage range, which improves dynamic behavior significantly at low

line and simplifies loop design. In fact, deriving a voltage proportional to the RMS line

voltage implies a form of integration, which has its own time constant. If it is too small the

voltage generated is affected by a considerable amount of ripple at twice the mains

frequency that causes distortion of the current reference (resulting in high THD and poor

PF); if it is too large there is a considerable delay in setting the right amount of feedforward,

resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in

response to large line voltage changes. Clearly a trade-off is required. The device realizes

Ω

max

MULT

multL

Ω

⋅

−

319

multL

multH

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