DocID025611 Rev 1

9/20

AN4414

Description of SMPS

20

As we know from Equation 10:

that is:

Equation 17

or

So one can use a higher switching frequency of the operation to maintain a lower

inductance and hence a lower number of primary turns.

operation.

Select VIPER17H for this application.

1.3

Calculations

Input voltage to converter: 80 V to 265 VAC

Maximum withstanding voltage: 440 VAC line-line.

Output voltage: Vout = 5 V

Maximum output current: Iout = 100 mA

Equation 18

Pout = Vout x Iout

The typical power stage to withstand this wide mains operation is to clamp the DC bus

voltage to the flyback stage at a lower level. This can be achieved by using a MOSFET and

a Zener clamp circuit as a front-end stage as shown in the schematic in Figure 9 on

page 17. This approach is a simple series pass regulator and well acceptable as we are

dealing with a very low power output requirements. The DC input to the flyback stage

doesn't exceed the voltage at which the Zener clamp network starts conducting and any

further increase in an input rectified voltage will drop across the series MOSFET. Since the

the heat on the copper area provided in the printed circuit board.

Minimum DC bus voltage at flyback input:

Equation 19

Vdcmin ~ 100 VDC.

Lp

2 Pout



 Ipkp

2

fsw





-----------------------------------------

=

Lp

 1

fsw

---------

Lp

 1

Bmax

----------------