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AN394 - APPLICATION NOTE

When the Q output is at a “zero” level (VOL= 0.4 V), during the overlap period, the R and Rp resistors form

a potential divider chain, as shown in Figure 9. Rp must have a resistance greater than 5 times that of R.

This means that the “zero” level on the D/Q bus is: 0.4 V + (5 V -0.4 V) x R / (R + Rp) = 1.17 V. Although

this value is 330 mV below the 1.5 V maximum input-low level for CMOS, it does mean losing the wide

noise margin that is traditionally associated with the CMOS specification.

Figure 9. D/Q Bus Configuration with Pull-up Resistor (Rp)

For a high to low transition, the Q on-chip output buffer has to discharge the bus capacitance through the

R resistor and to sink some current from Vcc through the Rp resistor. The new time constant, when com-

pared to that calculated earlier in this document, is reduced by 17%, because of the parallel combination

of R and Rp. However, the steady low level is not 0.4 V, as had been assumed for TTL levels, but 1.17 V,

as calculated above for Rp = 5xR. Despite this smaller time constant, the voltage swing between high and

low is greater in this case, as described later in this document, so it is advisable to keep the same delay

(3xRC) between the C clock rising edge and the first sampling of the data line.

A greater problem is faced during the low to high transition, though. At first, the bus capacitance is charged

by the Q output through R, and from the Vcc power supply via Rp, again leading to a time constant for Rp

connected in parallel with R. But once the D/Q bus reaches the Q output voltage level, the Q on-chip buffer

automatically turns off, and the Rp resistor remains the only contributor to the charge of the bus capaci-

tance. This results in a much higher time constant: RpxC =5xRC.

For the worst case output-high level for Q (VOH= 2.4 V), combined with the minimum input-high level for

CMOS, the charging delay, after the Q driver cuts out, needs to be at least 0.55xRpC: that is, 2.75xRC.

This is still assuming Vcc = 5 V, and allowing for a noise margin of 300 or 400 mV.

As a result, the minimum delay between the rising edge of C and the sampling of the D/Q bus should be

2 or 3 times longer than the one we have found for the TTL levels (without Rp), and the clock frequency

must be reduced accordingly. (A typical oscilloscope plot is shown in Figure 10).

It is possible to avoid this situation by using a TTL-compatible CMOS device as the Q receiver circuit, and

thereby to remove the need for the Rp resistor. Suitable devices include:

s

members of the 74HCTXXX family

s

a CMOS microcontroller that provides an option for “TTL input levels” on its I/O ports, such as the ST9

series.

Ai02423

EEPROM Device

D

Q

Data In

D Driver

(CMOS)

Output

Buffer

R

RP

VCC

Driver Enable

(active low)

Data Out

Q Receiver

(CMOS)