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AN2549 Datasheet(PDF) 24 Page - STMicroelectronics

Part # AN2549
Description  Porting an application from the ST10F269Zx to the ST10F272Z2
PDF  33 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2549 Datasheet(HTML) 24 Page - STMicroelectronics

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AN2549
New registers
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4.1.2
Software impact
On ST10F272Z2, this register must be programmed by the user before accessing XRAM2
so that:
●
RGSZ defines a 16 Kbyte window size. RGSZ = 0110b
●
RGSAD defines bits 8 to 19 of the window start address aligned to a 16-Kbyte
boundary (the least significant bits of the field are not relevant).
In the ST10F272Z2, the XRAM2 cannot be located within page 3 of segment 0. The user
can either:
●
map the XRAM2 from anywhere above address 09’0000h
●
map the XRAM2 in the 16-Kbyte page available in segment 0 in the 00’8000h -
00’BFFFh range.
The desired value should be written in XADRS3 register before enabling XRAM2 in the
SYSCON and XPERCON registers.
Note:
XADRS3 cannot be changed after executing the EINIT instruction.
Example
To map the 16-Kbyte XRAM2 onto page 60 (starting address 0F’0000h, compatible
with the ST10F276E), then XADRS3 must be initialized with the value F006h.
To map the 16-Kbyte XRAM2 onto page 2 (starting address 00’8000h), then XADRS3
must be initialized with the value 0806h.
Variables and PEC transfers
For architecture reasons, the PEC destination and source pointers must be in the segment
0. Therefore, all RAM variables and arrays that are PEC-addressed must be located in RAM
memory available in segment 0 (DPRAM + XRAM1, and XRAM2 if remapped onto page 3).
About Toolchain memory model
A change in the Toolchain configuration is needed to take into account the XRAM2’s new
location. In the ST10F269Zx, all the XRAM is in page 3 and it is then automatically
addressed using DPP3 that points to page 3 (in order to access the DPRAM and the
SFR/ESFR). For the ST10F272Z2, it is necessary to dedicate a DPP to access some of
XRAM2.
Example in case of Small memory model with tasking toolchain
The Small memory model makes it possible to have a total code size up to 16 Mbytes, up to
64 Kbytes of fast accessible 'normal user data' in three different memory configurations and
the possibility to access far/huge data, if more than 64 Kbytes of data is needed.



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