AN2555 - Application note

Modified features

5/33

Software impact

In case the optional 32 kHz is not used, the OFF32 bit of the RTCCON register must be set. Prior to

setting the OFF32 bit in RTCCON register, the RTC must be enabled by setting RTCEN, bit 4 of

XPERCON, and XPEN, bit 3 of SYSCON.

1.2

XRAM

The ST10F269Zx has 10 Kbytes of extension RAM whereas the ST10F276Z5 has 66 Kbytes.

The XRAM of the ST10F269Zx is divided into 2 ranges, XRAM1 of 2 Kbytes and XRAM2 of 8 Kbytes:

●

The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN, bit 2 of

SYSCON register and of XPERCON register, respectively, must both be set).

●

The XRAM2 address range is 00’C000h - 00’DFFFh if enabled (XPEN and XRAM2EN, bit 2 of

SYSCON register and bit 3 of XPERCON register, respectively, must both be set).

The XRAM of the ST10F276Z5 is divided into 2 ranges, XRAM1 of 2 Kbytes and XRAM2 of 64 Kbytes:

●

The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN, bit 2 of

SYSCON register and bit 2 of XPERCON register, respectively, must both be set).

●

The XRAM2 address range is 0F’0000h - 0F’FFFFh if enabled (XPEN and XRAM2EN, bit 2 of

SYSCON register and bit 3 of XPERCON register, respectively, must both be set).

1.2.1

Hardware impacts

None.

1.2.2

Software impacts

There is no change in the enabling of the XRAM blocks: XPERCON register bits, XRAM1EN and

XRAM2EN, and SYSCON register bit, XPEN, are used to enable them.

The memory mapping of the application is impacted by the different XRAM size and the different location

of XRAM2 in segment 15. In the ST10F269Zx the whole XRAM is in page 3 of segment 0.

Variables and PEC transfers

For architecture reasons, the PEC destination and source pointers must be in segment 0. Therefore all

RAM variables and arrays that will be PEC addressed must be located within either the DPRAM

(00’F600h - 00’FDFFh) or XRAM1 (00’E000h - 00’E7FFh).

About Toolchain memory model

A change in the Toolchain configuration is needed to take into account the new XRAM2 location. In the

ST10F269Zx, the entire XRAM is in page 3 and is then automatically addressed using DPP3 that points

to page 3 (in order to access the DPRAM and the SFR/ESFR). For the ST10F276Z5, it is necessary to

dedicate a DPP to access some of XRAM2.

Example in case of Small Memory Model with Tasking toolchain

The Small memory model makes it possible to have a total code size up to 16 Mbytes, up to 64 Kbytes of

fast accessible 'normal user data' in three different memory configurations and the possibility to access

far/huge data, if more than 64 Kbytes of data is needed.