AN2633 datasheet(9/48 Pages) STMICROELECTRONICS

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AN2633

Power supply and clocks

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1.3.4

PLL

As shown in Figure 2, the oscillator input clock (fOSC) is the input clock to the programmable

PLL frequency multiplier. When the PLL is active, it generates an output frequency (fPLL)

according to the following equation:

Where the values of M, N and P must satisfy the following constraints:

You program the M, N and P values by writing to the PLL configuration register

(SCU_PLLCONF).

Care is required when programming the PLL multiplier and divider factors, not to exceed the

maximum allowed operation frequency (96 MHz).

At power up, the CPU defaults to run on the oscillator clock, as the PLL is not ready (locked).

The CPU can switch to the PLL clock only after the LOCK bit in the System status register

(SCU_SYSSTATUS) is set. In Sleep mode, the PLL is turned off. When waking up from

sleep mode if the fMSTR is selected to run off the PLL, the CPU waits until the LOCK bit is

set before it starts to run.

The LOCK bit is set when the PLL clock has stabilized (locked status) and maintains this

value as long as the PLL is locked. You can select the PLL clock as fMSTR clock source only

when the LOCK bit is 1. If the LOCK bit goes to 0 if for any reason, the PLL loses the

programmed frequency in which it was locked. In this case, the LOCK_LOST bit is set and

fMSTR automatically switches back to fOSC. fPLL is restored as the fMSTR source when the

LOCK bit becomes 1 again.

The LOCK and LOCK_LOST events can be configured to generate interrupt requests to the

VIC.

PLL

OSC

() M2

()

⁄

255

≤≤

255

≤≤

0P5

≤≤

1MHz

OSC M2MHz

≤

⁄

≤

200MHz

OSC

() M

⁄

622MHz

≤≤

4MHz

OSC

25MHz

≤≤

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