AN2633 datasheet(16/48 Pages) STMICROELECTRONICS

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Power supply and clocks

AN2633

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N_dummy_Instr = (fcpuclk/fosc_x1)*12 if (fcpuclk/fosc_x1)>=1

N_dummy_Instr = 3 if (fcpuclk/fosc_x1)<1

The worst case is represented by the core working out at the PLL maximum frequency (96

MHz) with an 4 MHz crystal or oscillator on the X1 inputs. In this case 288 dummy

instructions would be needed.

Sleep mode with a crystal connected to X1_CPU input

In order to cut the power consumption due to oscillation, the crystal inputs are disabled

during Sleep mode. During recovery from Sleep mode the oscillator takes a start-up time to

re-start the oscillation (Refer to the datasheet for the start-up time). For this reason, when a

crystal is connected to the crystal inputs, the system clock source must be switched

to the RTC clock before entering Sleep mode. After waking up, the CPU runs on the RTC

clock and needs to wait until the crystal start-up time elapses before switching back to the

oscillator or PLL clock (Refer to STR91xFA Reference Manual for more information about

Clock Management during Sleep mode with crystal connected).

Sleep mode with an oscillator connected to X1_CPU input

In this case, the oscillation restarts right away after the X1 inputs are re-enabled and it is not

necessary to switch to RTC clock before entering Sleep mode.

Sleep mode with the PLL used as system clock source

If the oscillation on the X1_CPU inputs is generated by a crystal the software has to

explicitly switch the system clock source to the RTC clock before entering Sleep mode and,

when exiting Sleep mode, switch back to the PLL only after the crystal start-up time.

During Sleep mode, the PLL is automatically turned off and the system clock is

automatically switched to the oscillator input. On exit from Sleep mode, the system clock

goes back to the PLL clock only after the PLL is locked.

If the oscillation on the X1_CPU input is generated by an oscillator no action needs to be

taken since the PLL is automatically turned off, the system clock is automatically connected

to the oscillator clock and changed back to the PLL clock after exiting from Sleep mode once

the PLL is locked (refer to STR91xFA Reference Manual for more information about Clock

Management during Sleep mode

with crystal and PLL).

Sleep mode entry timing

When Sleep mode is selected, all the clock circuits and the oscillator pad (4-25 MHz) are

turned off. This procedure is controlled by a dedicated State Machine inside the Power

Management Unit (PMU), in order to switch off the clocks safely.

During the Sleep mode sequence, there are many interactions between the Power

Management Unit (PMU) and the Clock Control Unit (CCU). In particular, when the low

power mode is set, a signal is asserted to gate the peripheral clocks. As response to this

signal, all the peripherals have to send back to the PMU the acknowledgement that the clock

was shut-off.

The setting or enabling of the peripheral clocks depends on the Clock control register

(SCU_CLKCNTR) configuration and on the EE bit setting in the Watchdog clock control

AN2633 Datasheet(PDF) 16 Page - STMicroelectronics

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