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UPD703003 Datasheet(PDF) 25 Page - NEC |
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UPD703003 Datasheet(HTML) 25 Page - NEC |
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25 / 82 page  25 µPD703003 Data Sheet U12261EJ2V1DS00 The configuration of the asynchronous serial interfaces 0, 1 (UART0, UART1) are shown below. Figure 9-1. Block Diagram of Asynchronous Serial Interfaces 0, 1 (UART0, UART1) Internal bus 16/8 Receive buffer 8 RXBn RXBnL Receive shift register Transmit shift register RXDn TXDn Reception control parity check Transmission control parity attachment 1 16 INTSRn INTSERn PEn FEn OVEn SOTn ASISn 16/8 TXSn TXSnL INTSTn 1 16 1 2 Baud rate generator 88 ASIMn0 ASIMn1 EBSn RXEn TXEn PSn1 PSn0 CLn SLn SCLSn φ Remark n = 0, 1 φ : internal system clock |
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