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UPD703003 Datasheet(PDF) 68 Page - NEC |
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UPD703003 Datasheet(HTML) 68 Page - NEC |
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68 / 82 page ![]() µPD703003 68 Data Sheet U12261EJ2V1DS00 (7) Bus hold timing (1/2) Parameter Symbol Conditions 25-MHz Version 33-MHz Version Units MIN. MAX. MIN. MAX. HLDRQ setup time (to CLKOUT ↓) <54> tSHQK 88 ns HLDRQ hold time (from CLKOUT ↓) <55> tHKHQ 55 ns CLKOUT ↑ → HLDAK delay time <56> tDKHA 20 20 ns HLDRQ high-level width <57> tWHQH T + 10 T + 10 ns HLDAK low-level width <58> tWHAL T – 10 T – 10 ns CLKOUT ↑ → bus float delay time <59> tDKF 20 20 ns HLDAK ↑ → bus output delay time <60> tDHAC –3 –3 ns HLDRQ ↓ → HLDAK↓ delay time <61> tDHQHA1 (2n + 7.5)T + 20 (2n + 7.5)T + 20 ns HLDRQ ↑ → HLDAK↑ delay time <62> tDHQHA2 0.5T 1.5T + 20 0.5T 1.5T + 20 ns Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function. |
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