UPD703003 datasheet(14/82 Pages) NEC

14 / 82 page

µPD703003

Data Sheet U12261EJ2V1DS00

3. FUNCTION BLOCKS

3.1 Internal Units

3.1.1 CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic

operations, data transfers, and almost all other instruction processing.

Other dedicated on-chip hardware, such as the multiplier (16 bits

× 16 bits) and the barrel shifter (32 bits) help

accelerate processing of complex instructions.

3.1.2 Bus control unit (BCU)

The BCU starts a required bus cycle based on the physical address obtained by the CPU. When an instruction

is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a

prefetch address and prefetches the instruction code. The prefetched instruction code is stored in a prefetch queue.

3.1.3 ROM

ROM is mapped to the address space starting at 00000000H. The MODE pin can be used to select an access

enable/disable setting. ROM can be accessed by the CPU in one clock cycle when an instruction is fetched.

3.1.4 RAM

RAM is mapped to the address space starting at FFFFE000H. RAM can be accessed by the CPU in one clock

cycle when data accessed.

3.1.5 Ports

In addition to the 75 pins (port 0 to port 11) comprising I/O ports (of which eight pins comprise an input-only port),

various port pin and control pin functions can be selected for these pins.

3.1.6 Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP110 to INTP113, INTP120 to INTP123, INTP130

to INTP133, and INTP140 to INTP143) from on-chip peripheral hardware and external hardware. Eight interrupt

priority levels can be specified for these interrupt requests, and multiplexed servicing control can be performed for

interrupt sources.

3.1.7 Clock generator (CG)

An on-chip PLL enables the CPU operating clock to be supplied to resonators connected to pins X1 and X2 at 5

frequency, 1

× frequency, and 1/2× frequency. It can also be connected to an external clock instead of to the resonator.

3.1.8 Real-time pulse unit (RPU)

The RPU includes a four-channel 16-bit timer/event counter and a one-channel 16-bit interval timer, which enables

measurement of pulse intervals and frequency as well as programmable pulse output.

UPD703003 Datasheet(PDF) 14 Page - NEC