UPD703003 datasheet(66/82 Pages) NEC

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µPD703003

Data Sheet U12261EJ2V1DS00

(6) Write timing (1/2)

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Units

MIN.

MAX.

MIN.

MAX.

CLKOUT

↑ → address delay time <20> tDKA

CLKOUT

↑ → R/W, UBEN, LBEN delay time <78> tDKA2

–2

+13

–2

+13

CLKOUT

↓ → ASTB delay time <22> tDKST

–2

+13

–2

+13

CLKOUT

↑ → DSTB delay time <23> tDKD

–2

+13

–2

+13

WAIT setup time (to CLKOUT

↓) <26> tSWTK

WAIT hold time (from CLKOUT

↓) <27> tHKWT

Address hold time (from CLKOUT

↑) <28> tHKA

Address setup time (to ASTB

↓) <29> tSAST

0.5T – 10

Address hold time (from ASTB

↓) <30> tHSTA

0.5T – 10

ASTB

↓ → DSTB↓ delay time

<34> tDSTD

0.5T – 10

DSTB

↑ → ASTB↑ delay time

<37> tDDSTH

0.5T – 10

DSTB low-level width

<39> tWDL

(1 + n)T – 10

ASTB high-level width

<40> tWSTH

T – 10

WAIT setup time (to address)

<41> tSAWT1

≥ 1

1.5T – 20

<42> tSAWT2

(1.5 + n)T – 20

WAIT hold time (from address)

<43> tHAWT1

≥ 1

(0.5 + n)T

<44> tHAWT2

(1.5 + n)T

WAIT setup time (to ASTB

↓)

<45> tSSTWT1

≥ 1

T – 15

<46> tSSTWT2

(1 + n)T – 15

WAIT hold time (from ASTB

↓)

<47> tHSTWT1

≥ 1nT

<48> tHSTWT2

(1 + n)T

CLKOUT

↑ → data output delay time <49> tDKOD

DSTB

↓ → data output delay time <50> tDDOD

Data output hold time (from CLKOUT

↑) <51> tHKOD

Data output setup time (to DSTB

↑) <52> tSODD

(1 + n)T – 15

Data output hold time (from DSTB

↑) <53> tHDOD

T – 10

Remarks 1. T = tCYK

2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may

vary when using the programmable wait insertion function.

UPD703003 Datasheet(PDF) 66 Page - NEC

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