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PIC17C752-08/P Datasheet(PDF) 309 Page - Microchip Technology |
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PIC17C752-08/P Datasheet(HTML) 309 Page - Microchip Technology |
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309 / 320 page  © 1997 Microchip Technology Inc. Preliminary DS30264A-page 309 PIC17C75X TMR1 .......................................................................... 45 TMR2 .......................................................................... 45 TMR3H........................................................................ 45 TMR3L ........................................................................ 45 TXREG1...................................................................... 44 TXREG2...................................................................... 45 TXSTA1 ...................................................................... 44 TXSTA2 ...................................................................... 45 WREG................................................................... 35, 44 Regsters TMR0L ........................................................................ 44 Reset Section ........................................................................ 21 Status Bits and Their Significance .............................. 23 Time-Out in Various Situations ................................... 23 Time-Out Sequence.................................................... 23 Restart Condition Enabled bit, RSE .................................. 126 RETFIE ............................................................................. 207 RETLW ............................................................................. 207 RETURN ........................................................................... 208 RLCF................................................................................. 208 RLNCF .............................................................................. 209 RRCF ................................................................................ 209 RRNCF ............................................................................. 210 RSE................................................................................... 126 RX Pin Sampling Scheme................................................. 115 S S........................................................................................ 124 SAE ................................................................................... 126 Sampling ........................................................................... 115 Saving STATUS and WREG in RAM .................................. 38 SCK................................................................................... 127 SCL ................................................................................... 135 SDA................................................................................... 135 SDI .................................................................................... 127 SDO .................................................................................. 127 Serial Clock, SCK ............................................................. 127 Serial Clock, SCL .............................................................. 135 Serial Data Address, SDA................................................. 135 Serial Data In, SDI ............................................................ 127 Serial Data Out, SDO........................................................ 127 SETF ................................................................................. 210 SFR ................................................................................... 184 SFR (Special Function Registers)....................................... 39 SFR As Source/Destination .............................................. 184 Signed Math .......................................................................... 9 Slave Select Synchronization ........................................... 130 Slave Select, SS ............................................................... 127 SLEEP ...................................................................... 180, 211 SMP .................................................................................. 124 Software Simulator (MPSIM) ............................................ 221 SPBRG ............................................................. 116, 120, 122 SPBRG1 ....................................................................... 25, 44 SPBRG2 ....................................................................... 25, 45 SPE ................................................................................... 126 Special Features of the CPU ............................................ 177 Special Function Registers ................................... 39, 44, 184 Summary..................................................................... 44 Special Function Registers, File Map ......................... 43, 273 SPI Master Mode ............................................................. 129 Serial Clock............................................................... 127 Serial Data In ............................................................ 127 Serial Data Out ......................................................... 127 Serial Peripheral Interface (SPI) ............................... 123 Slave Select.............................................................. 127 SPI clock................................................................... 129 SPI Mode.................................................................. 127 SPI Clock Edge Select, CKE ............................................ 124 SPI Data Input Sample Phase Select, SMP ..................... 124 SPI Master/Slave Connection........................................... 130 SPI Module Master/Slave Connection ......................................... 130 Slave Mode............................................................... 130 Slave Select Synchronization ................................... 130 Slave Synch Timnig.................................................. 131 Slave Timing with CKE = 0 ....................................... 132 Slave Timing with CKE = 1 ....................................... 133 SS ..................................................................................... 127 SSP .................................................................................. 123 Block Diagram (SPI Mode) ....................................... 128 SPI Mode.................................................................. 127 SSPADD........................................................... 134, 135 SSPBUF ........................................................... 129, 134 SSPCON1 ................................................................ 125 SSPCON2 ................................................................ 126 SSPSR ............................................................. 129, 135 SSPSTAT ......................................................... 124, 134 SSP I2C SSP I2C Operation ................................................... 134 SSP Module SPI Master Mode...................................................... 129 SPI Master./Slave Connection.................................. 130 SPI Slave Mode........................................................ 130 SSPCON1 Register .................................................. 134 SSP Overflow Detect bit, SSPOV..................................... 135 SSPADD ..............................................................................46 SSPBUF ............................................................. 46, 134, 135 SSPCON1 .......................................................... 46, 125, 134 SSPCON2 .................................................................. 46, 126 SSPEN ..................................................................... 125, 290 SSPIE ..................................................................................32 SSPIF ......................................................................... 34, 136 SSPM3:SSPM0 ........................................................ 125, 290 SSPOV ..................................................... 125, 135, 152, 290 SSPSTAT ........................................................... 46, 124, 134 Stack Operation.....................................................................50 Pointer .........................................................................50 Stack............................................................................39 Start bit (S) ....................................................................... 124 Start Condition Enabled bit, SAE...................................... 126 STKAV .......................................................................... 48, 50 Stop bit (P)........................................................................ 124 Stop Condition Enable bit ................................................. 126 SUBLW ............................................................................. 211 SUBWF............................................................................. 212 SUBWFB .......................................................................... 212 SWAPF ............................................................................. 213 Synchronous Master Mode............................................... 117 Synchronous Master Reception ....................................... 119 Synchronous Master Transmission .................................. 117 Synchronous Serial Port ................................................... 123 Synchronous Serial Port Enable bit, SSPEN............ 125, 290 Synchronous Serial Port Interrupt .......................................34 Synchronous Serial Port Interrupt Enable, SSPIE...............32 Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 ........................................................ 125, 290 Synchronous Slave Mode................................................. 121 T T0CKI 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