PIC17C752-08SLASHP datasheet(313/320 Pages) MICROCHIP

313 / 320 page

Preliminary

DS30264A-page 313

PIC17C75X

Figure 10-1:

RA0 and RA1 Block Diagram ..................... 65

Figure 10-2:

RA2 Block Diagram .................................... 66

Figure 10-3:

RA3 Block Diagram .................................... 66

Figure 10-4:

RA4 and RA5 Block Diagram ..................... 66

Figure 10-5:

Block Diagram of RB5:RB4 and RB1:RB0

Port Pins ..................................................... 68

Figure 10-6:

Block Diagram of RB3:RB2 Port Pins......... 69

Figure 10-7:

Block Diagram of RB6 Port Pin................... 70

Figure 10-8:

Block Diagram of RB7 Port Pin................... 70

Figure 10-9:

Block Diagram of RC7:RC0 Port Pins ........ 72

Figure 10-10: Block Diagram of RD7:RD0 Port Pins

(in I/O Port Mode) ....................................... 74

Figure 10-11: Block Diagram of RE2:RE0 (in I/O Port

Mode).......................................................... 76

Figure 10-12: Block Diagram of RE3/CAP4 Port Pin ........ 77

Figure 10-13: Block Diagram of RF7:RF0......................... 78

Figure 10-14: Block Diagram of RG3:RG0........................ 80

Figure 10-15: RG4 Block Diagram .................................... 81

Figure 10-16: RG7:RG5 Block Diagram............................ 81

Figure 10-17: Successive I/O Operation ........................... 83

Figure 12-1:

T0STA Register (Address: 05h,

Unbanked) .................................................. 87

Figure 12-2:

Timer0 Module Block Diagram ................... 88

Figure 12-3:

TMR0 Timing with External Clock

(Increment on Falling Edge) ....................... 88

Figure 12-4:

TMR0 Timing: Write High or Low Byte ....... 89

Figure 12-5:

TMR0 Read/Write in Timer Mode ............... 90

Figure 13-1:

TCON1 Register (Address: 16h, Bank 3) ... 91

Figure 13-2:

TCON2 Register (Address: 17h, Bank 3) ... 92

Figure 13-3:

TCON3 Register (Address: 16h, Bank 7) ... 93

Figure 13-4:

Timer1 and Timer2 in Two 8-bit Timer/

Counter Mode ............................................. 94

Figure 13-5:

TMR2 and TMR1 in 16-bit Timer/Counter

Mode........................................................... 95

Figure 13-6:

Simplified PWM Block Diagram .................. 97

Figure 13-7:

PWM Output ............................................... 97

Figure 13-8:

Timer3 with three Capture and One

Period Register Block Diagram................. 100

Figure 13-9:

Timer3 with Four Captures Block

Diagram .................................................... 102

Figure 13-10: Timer1, Timer2, and Timer3 Operation

(in Counter Mode)..................................... 104

Figure 13-11: Timer1, Timer2, and Timer3 Operation

(in Timer Mode) ........................................ 105

Figure 14-1:

TXSTA1 Register (Address: 15h, Bank 0)

TXSTA2 Register (Address: 15h, Bank 4) 107

Figure 14-2:

RCSTA1 Register (Address: 13h, Bank 0)

RCSTA2 Register (Address: 13h, Bank 4) 108

Figure 14-3:

USART Transmit....................................... 109

Figure 14-4:

USART Receive........................................ 109

Figure 14-5:

Asynchronous Master Transmission......... 114

Figure 14-6:

Asynchronous Master Transmission

(Back to Back) .......................................... 114

Figure 14-7:

RX Pin Sampling Scheme ........................ 115

Figure 14-8:

Asynchronous Reception.......................... 116

Figure 14-9:

Synchronous Transmission ...................... 118

Figure 14-10: Synchronous Transmission

(Through TXEN) ....................................... 118

Figure 14-11: Synchronous Reception (Master Mode,

SREN)....................................................... 119

Figure 15-1:

SPI Mode Block Diagram.......................... 123

Figure 15-2:

I2C Slave Mode Block Diagram ................ 123

Figure 15-3:

I2C Master Mode Block Diagram .............. 123

Figure 15-4:

SSPSTAT: Sync Serial Port Status

Figure 15-5:

SSPCON1: Sync Serial Port Control

Register1 (Address 11h, BANK 6)............ 125

Figure 15-6:

SSPCON2: Sync Serial Port Control

Register2 (Address 12h, BANK 6)........... 126

Figure 15-7:

SSP Block Diagram (SPI Mode)............... 128

Figure 15-8:

SPI Mode Timing (Master Mode) ............. 129

Figure 15-9:

SPI Master/Slave Connection .................. 130

Figure 15-10: Slave Synchronization Timing .................. 131

Figure 15-11: SPI Mode Timing (Slave Mode with

CKE = 0)................................................... 132

Figure 15-12: SPI Mode Timing (Slave Mode with

CKE = 1)................................................... 133

Figure 15-13: SSP Block Diagram

(I2C Mode)................................................ 134

Figure 15-14: I2C Master Mode Block Diagram.............. 134

Figure 15-15: I2C Waveforms for Reception

(7-bit Address).......................................... 136

Figure 15-16: I2C Waveforms for Transmission

(7-bit Address).......................................... 136

Figure 15-17: I2C Slave-Transmitter (10-bit Address).... 137

Figure 15-18: I2C Slave-Receiver (10-bit Address)........ 138

Figure 15-19: General Call Address Sequence

(7 or 10-bit Mode)..................................... 139

Figure 15-20: SSP Block Diagram (I2C Master Mode) ... 141

Figure 15-21: Baud Rate Generator Block Diagram....... 143

Figure 15-22: Baud Rate Generator Timing With

Clock Arbitration ....................................... 143

Figure 15-23: First Start Bit Timing................................. 144

Figure 15-24: Start Condition FlowChart ........................ 145

Figure 15-25: Repeat Start Condition Timing ................. 146

Figure 15-26: Restart Condition FlowChart (page 1)...... 147

Figure 15-27: Restart Condition FlowChart (page 2)...... 148

Figure 15-28: Master Transmit FlowChart ...................... 150

Figure 15-29: I2C Master Mode Timing (Transmission,

7 or 10-bit Address).................................. 151

Figure 15-30: Master Receiver FlowChart...................... 153

Figure 15-31: I2C Master Mode Timing (Reception

7-Bit Address)........................................... 154

Figure 15-32: Acknowledge Sequence Timing ............... 155

Figure 15-33: Acknowledge FlowChart........................... 156

Figure 15-34: Stop Condition Receive or Transmit

Mode ........................................................ 157

Figure 15-35: Stop Condition FlowChart ........................ 158

Figure 15-36: Clock Arbitration Timing in Master

Transmit Mode ......................................... 159

Figure 15-37: Bus Collision Timing for Transmit and

Acknowledge ............................................ 160

Figure 15-38: Bus Collision During Start Condition

(SDA only) ................................................ 161

Figure 15-39: Bus Collision During Start Condition

(SCL = 0) .................................................. 162

Figure 15-40: BRG Reset Due to SDA Collision During

Start Condition.......................................... 162

Figure 15-41: Bus Collision During a Restart Condition

(Case 1).................................................... 163

Figure 15-42: Bus Collision During Restart Condition

(Case 2).................................................... 163

Figure 15-43: Bus Collision During a Stop Condition

(Case 1).................................................... 164

Figure 15-44:

Bus Collision During a Stop Condition

(Case 2).................................................... 164

Figure 15-45: Sample device configuration for I2C bus .. 165

Figure 16-1:

ADCON0 Register (Address: 14h,

Bank 5) ..................................................... 167

Figure 16-2:

ADCON1 Register (Address 15h,

Bank 5) ..................................................... 168

PIC17C752-08/P Datasheet(PDF) 313 Page - Microchip Technology

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