PIC17C752-08SLASHP datasheet(314/320 Pages) MICROCHIP

314 / 320 page

PIC17C75X

DS30264A-page 314

Preliminary

Figure 16-3:

A/D Block Diagram ................................... 169

Figure 16-4:

Analog Input Model ................................... 170

Figure 16-5:

A/D Result Justification ............................. 173

Figure 16-6:

A/D Transfer Function............................... 174

Figure 16-7:

Flowchart of A/D Operation ...................... 175

Figure 17-1:

Configuration Words ................................. 177

Figure 17-2:

Watchdog Timer Block Diagram ............... 179

Figure 17-3:

Wake-up From Sleep Through Interrupt ... 180

Figure 17-4:

Typical In-Circuit Serial Programming

Connection................................................ 182

Figure 18-1:

General Format for Instructions ................ 184

Figure 18-2:

Q Cycle Activity......................................... 185

Figure 20-1:

Parameter Measurement Information ....... 231

Figure 20-2:

External Clock Timing ............................... 232

Figure 20-3:

CLKOUT and I/O Timing........................... 233

Figure 20-4:

Reset, Watchdog Timer, Oscillator Start-up

Timer, Power-up Timer, and Brown-out

Reset Timing............................................. 234

Figure 20-5:

Timer0 External Clock Timings ................. 235

Figure 20-6:

Timer1, Timer2, and Timer3 External

Clock Timings ........................................... 235

Figure 20-7:

Capture Timings ....................................... 236

Figure 20-8:

PWM Timings ........................................... 236

Figure 20-9:

SPI Master Mode Timing (CKE = 0) ......... 237

Figure 20-10: SPI Master Mode Timing (CKE = 1) ......... 238

Figure 20-11: SPI Slave Mode Timing (CKE = 0) ........... 239

Figure 20-12: SPI Slave Mode Timing (CKE = 1) ........... 240

Figure 20-13: I2C Bus Start/Stop Bits Timing.................. 241

Figure 20-14: I2C Bus Data Timing ................................. 242

Figure 20-15: USART Synchronous Transmission

(Master/Slave) Timing............................... 244

Figure 20-16: USART Synchronous Receive

(Master/Slave) Timing............................... 244

Figure 20-17: A/D Conversion Timing ............................. 246

Figure 20-18: Memory Interface Write Timing................. 247

Figure 20-19: Memory Interface Read Timing ................ 248

Figure 21-1:

Typical RC Oscillator Frequency vs.

Temperature ............................................. 249

Figure 21-2:

Typical RC Oscillator Frequency vs. VDD . 250

Figure 21-3:

Typical RC Oscillator Frequency vs. VDD . 250

Figure 21-4:

Typical RC Oscillator Frequency vs. VDD . 251

Figure 21-5:

Transconductance (gm) of LF Oscillator

vs. VDD...................................................... 252

Figure 21-6:

Transconductance (gm) of XT Oscillator

vs. VDD...................................................... 252

Figure 21-7:

Typical IDD vs. Frequency (External

Clock 25

°C)............................................... 253

Figure 21-8:

Maximum IDD vs. Frequency (External Clock

125

°C to -40°C) ........................................ 253

Figure 21-9:

Typical IPD vs. VDD Watchdog Disabled

°C.......................................................... 254

Figure 21-10: Maximum IPD vs. VDD Watchdog

Disabled .................................................... 254

Figure 21-11: Typical IPD vs. VDD Watchdog Enabled

°C.......................................................... 255

Figure 21-12: Maximum IPD vs. VDD Watchdog

Enabled..................................................... 255

Figure 21-13: WDT Timer Time-Out Period vs. VDD ....... 256

Figure 21-14: IOH vs. VOH, VDD = 3V .............................. 256

Figure 21-15: IOH vs. VOH, VDD = 5V .............................. 257

Figure 21-16: IOL vs. VOL, VDD = 3V ............................... 257

Figure 21-17: IOL vs. VOL, VDD = 5V ............................... 258

Figure 21-18: VTH (Input Threshold Voltage) of I/O Pins

(TTL) VS. VDD............................................ 258

Figure 21-19: VIH, VIL of I/O Pins (Schmitt Trigger) VS.

VDD ........................................................... 259

Figure 21-20: VTH (Input Threshold Voltage) of OSC1

Input (In XT and LF Modes) vs. VDD ....... 259

Figure E-1:

Start and Stop Conditions ........................ 267

Figure E-2:

7-bit Address Format ................................ 268

Figure E-3:

I2C 10-bit Address Format........................ 268

Figure E-4:

Slave-receiver Acknowledge .................... 268

Figure E-5:

Data Transfer Wait State .......................... 268

Figure E-6:

Master-transmitter Sequence ................... 269

Figure E-7:

Master-receiver Sequence ....................... 269

Figure E-8:

Combined Format..................................... 269

Figure E-9:

Multi-master Arbitration

(Two Masters) .......................................... 270

Figure E-10:

Clock Synchronization .............................. 270

Figure E-11:

I2C Bus Start/Stop Bits Timing

Specification ............................................. 271

Figure E-12:

I2C Bus Data Timing Specification .......... 272

Figure F-1:

PIC17C75X Register File Map ................. 273

Figure F-2:

ALUSTA Register (Address: 04h,

Unbanked) ................................................ 274

Figure F-3:

T0STA Register (Address: 05h,

Unbanked) ................................................ 275

Figure F-4:

CPUSTA Register (Address: 06h,

Unbanked) ................................................ 276

Figure F-5:

INTSTA Register (Address: 07h,

Unbanked) ................................................ 277

Figure F-6:

PIE1 Register (Address: 17h, Bank 1) ..... 278

Figure F-7:

PIE2 Register (Address: 11h, Bank 4) ..... 279

Figure F-8:

PIR1 Register (Address: 16h, Bank 1) ..... 280

Figure F-9:

PIR2 Register (Address: 10h, Bank 4) ..... 281

Figure F-10:

TXSTA1 Register (Address: 15h, Bank 0)

TXSTA2 Register (Address: 15h,

Bank 4) ..................................................... 282

Figure F-11:

RCSTA1 Register (Address: 13h,

Bank 0)

RCSTA2 Register (Address: 13h,

Bank 4) ..................................................... 283

Figure F-12:

TCON1 Register (Address: 16h,

Bank 3) ..................................................... 284

Figure F-13:

TCON2 Register (Address: 17h,

Bank 3) ..................................................... 285

Figure F-14:

TCON3 Register (Address: 16h,

Bank 7) ..................................................... 286

Figure F-15:

ADCON0 Register (Address: 14h,

Bank 5) ..................................................... 287

Figure F-16:

ADCON1 Register (Address 15h,

Bank 5) ..................................................... 288

Figure F-17:

SSPSTAT: Sync Serial Port Status

Figure F-18:

SSPCON1: Sync Serial Port Control

Figure F-19:

SSPCON2: Sync Serial Port Control

Register2 (Address 12h, BANK 6)........... 291

PIC17C752-08/P Datasheet(PDF) 314 Page - Microchip Technology

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