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PIC17C752-08/P Datasheet(PDF) 312 Page - Microchip Technology |
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PIC17C752-08/P Datasheet(HTML) 312 Page - Microchip Technology |
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312 / 320 page ![]() PIC17C75X DS30264A-page 312 Preliminary © 1997 Microchip Technology Inc. List of Equations and Examples Example 3-1: Signed Math.................................................. 9 Example 4-1: Instruction Pipeline Flow ............................. 19 Example 6-1: Saving STATUS and WREG in RAM (Simple) ...................................................... 37 Example 6-2: Saving STATUS and WREG in RAM (Nested) ...................................................... 38 Example 7-1: Indirect Addressing ..................................... 51 Example 8-1: Table Write ................................................. 58 Example 8-2: Table Read ................................................. 60 Example 9-1: 8 x 8 Unsigned Multiply Routine ................. 61 Example 9-2: 8 x 8 Signed Multiply Routine ..................... 61 Equation 9-1: 16 x 16 Unsigned Multiplication Algorithm .. 62 Example 9-3: 16 x 16 Unsigned Multiply Routine ............. 62 Equation 9-2: 16 x 16 Signed Multiplication Algorithm ...... 63 Example 9-4: 16 x 16 Signed Multiply Routine ................. 63 Example 10-1: Initializing PORTA....................................... 66 Example 10-2: Initializing PORTB....................................... 69 Example 10-3: Initializing PORTC ...................................... 72 Example 10-4: Initializing PORTD ...................................... 74 Example 10-5: Initializing PORTE....................................... 76 Example 10-6: Initializing PORTF ....................................... 78 Example 10-7: Initializing PORTG ...................................... 80 Example 10-8: Read Modify Write Instructions on an I/O Port ....................................................... 83 Example 12-1: 16-Bit Read ................................................. 89 Example 12-2: 16-Bit Write ................................................. 89 Example 13-1: Sequence to Read Capture Registers ...... 103 Example 13-2: Writing to TMR3 ........................................ 104 Example 13-3: Reading from TMR3 ................................. 104 Example 14-1: Calculating Baud Rate Error ..................... 110 Example 15-1: Loading the SSPBUF (SSPSR) Register.. 127 Equation 16-1: A/D Minimum Charging Time (For CHOLD) .............................................. 170 Example 16-1: Calculating the Minimum Required Acquisition Time ....................................... 171 Example 16-2: A/D Conversion......................................... 172 List of Figures Figure 3-1: PIC17C75X Block Diagram ........................ 10 Figure 4-1: Oscillator / Resonator Start-up Characteristics............................................ 15 Figure 4-2: Crystal or Ceramic Resonator Operation (XT or LF OSC Configuration) .................... 16 Figure 4-3: Crystal Operation, Overtone Crystals (XT OSC Configuration) ............................. 16 Figure 4-4: External Clock Input Operation (EC OSC Configuration) ............................................. 17 Figure 4-5: External Parallel Resonant Crystal Oscillator Circuit ......................................... 17 Figure 4-6: External Series Resonant Crystal Oscillator Circuit ......................................... 17 Figure 4-7: RC Oscillator Mode .................................... 18 Figure 4-8: Clock/Instruction Cycle ............................... 19 Figure 5-1: Simplified Block Diagram of On-chip Reset Circuit ............................................... 21 Figure 5-2: Using On-Chip POR ................................... 22 Figure 5-3: External Power-On Reset Circuit (For Slow VDD Power-Up) .......................... 22 Figure 5-4: Oscillator Start-Up Time ............................. 22 Figure 5-5: Time-Out Sequence on Power-Up (MCLR Tied to VDD) ................................... 24 Figure 5-6: Time-Out Sequence on Power-Up (MCLR NOT Tied to VDD)........................... 24 Figure 5-7: Slow Rise Time (MCLR Tied to VDD) ......... 24 Figure 5-8: External Brown-out Protection Circuit 1 ..... 28 Figure 5-9: External Brown-out Protection Circuit 2 ..... 28 Figure 5-10: Brown-out Situations .................................. 28 Figure 6-1: Interrupt Logic ............................................ 29 Figure 6-2: INTSTA Register (Address: 07h, Unbanked) .................................................. 30 Figure 6-3: PIE1 Register (Address: 17h, Bank 1) ....... 31 Figure 6-4: PIE2 Register (Address: 11h, Bank 4) ....... 32 Figure 6-5: PIR1 Register (Address: 16h, Bank 1) ....... 33 Figure 6-6: PIR2 Register (Address: 10h, Bank 4) ....... 34 Figure 6-7: INT Pin / T0CKI Pin Interrupt Timing .......... 36 Figure 7-1: Program Memory Map and Stack............... 39 Figure 7-2: Memory Map in Different Modes ................ 40 Figure 7-3: External Program Memory Access Waveforms ................................................. 41 Figure 7-4: Typical External Program Memory Connection Diagram................................... 41 Figure 7-5: PIC17C75X Register File Map ................... 43 Figure 7-6: ALUSTA Register (Address: 04h, Unbanked) .................................................. 47 Figure 7-7: CPUSTA Register (Address: 06h, Unbanked) .................................................. 48 Figure 7-8: T0STA Register (Address: 05h, Unbanked) .................................................. 49 Figure 7-9: Indirect Addressing..................................... 50 Figure 7-10: Program Counter Operation ....................... 52 Figure 7-11: Program Counter using The CALL and GOTO Instructions ....................................... 52 Figure 7-12: BSR Operation ........................................... 53 Figure 8-1: TLWT Instruction Operation ........................ 55 Figure 8-2: TABLWT Instruction Operation .................... 55 Figure 8-3: TLRD Instruction Operation ........................ 56 Figure 8-4: TABLRD Instruction Operation .................... 56 Figure 8-5: TABLWT Write Timing (External Memory)... 58 Figure 8-6: Consecutive TABLWT Write Timing (External Memory) ...................................... 59 Figure 8-7: TABLRD Timing........................................... 60 Figure 8-8: TABLRD Timing (Consecutive TABLRD Instructions) ................................................ 60 |
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