PIC17C752-08SLASHP datasheet(170/320 Pages) MICROCHIP

170 / 320 page

PIC17C75X

DS30264A-page 170

Preliminary

16.1 A/D Acquisition Requirements

For the A/D converter to meet its speciﬁed accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 16-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD),

Figure 16-4. The source impedance affects the offset

voltage at the analog input (due to pin leakage current).

The maximum recommended impedance for ana-

log sources is 10 kΩ.After the analog input channel is

selected (changed) this acquisition must be done

before the conversion can be started.

calculate

the

minimum

acquisition

time,

Equation 16-1 may be used. This equation calculates

the acquisition time to within 1/2 LSb error (1024 steps

for the A/D). The 1/2 LSb error is the maximum error

allowed for the A/D to meet its speciﬁed accuracy.

EQUATION 16-1: A/D MINIMUM CHARGING

TIME (FOR CHOLD)

VHOLD = (VREF - (VREF/2048)) • (1 - e(-Tcap/C

HOLD

(RIC + RSS + RS)))

given

VHOLD = (VREF/2048), for 1/2 LSb resolution

VREF = VREF+ - VREF-

Tcap = -(200 pF)(1 k

Ω + RSS + RS) ln(1/2047)

Example 16-1 shows the calculation of the minimum

required acquisition time TACQ. This calculation is

based on the following application system assump-

tions.

CHOLD = 200 pF

Rs = 10 k

Ω

1/2 LSb error

VDD = 5V

→ Rss = 7 kΩ

Temp (application system max.) = 50

°C

VHOLD = 0 @ t = 0

Note 1: The reference voltage (VREF) has no

effect on the equation, since it cancels

itself out.

Note 2: The charge holding capacitor (CHOLD) is

not discharged after each conversion.

Note 3: The maximum recommended impedance

for analog sources is 10 k

Ω. This is

required to meet the pin leakage speciﬁ-

cation.

Note 4: After a conversion has completed, a

2.0TAD delay must complete before acqui-

sition can begin again. During this time the

holding capacitor is not connected to the

selected A/D input channel.

FIGURE 16-4: ANALOG INPUT MODEL

CPIN

ANx

5 pF

VDD

VT = 0.6V

I leakage

RIC

≤ 1k

Sampling

Switch

RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

5 6 7 8 9 10 11

( k

Ω )

VDD

= 200 pF

± 500 nA

Legend CPIN

I leakage

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

PIC17C752-08/P Datasheet(PDF) 170 Page - Microchip Technology

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