MT48LC2M32B2 datasheet(2/53 Pages) MICRON

2 / 53 page

64Mb: x32 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02

64Mb: x32

SDRAM

The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

page, with a burst terminate option. An auto precharge

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst se-

quence.

The 64Mb SDRAM uses an internal pipelined archi-

tecture to achieve high-speed operation. This archi-

tecture is compatible with the 2n rule of prefetch archi-

tectures, but it also allows the column address to be

changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while ac-

cessing one of the other three banks will hide the

precharge cycles and provide seamless, high-speed,

random-access operation.

The 64Mb SDRAM is designed to operate in 3.3V,

low-power memory systems. An auto refresh mode is

provided, along with a power-saving, power-down

mode. All inputs and outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM oper-

ating performance, including the ability to synchro-

nously burst data at a high data rate with automatic

column-address generation, the ability to interleave

between internal banks to hide precharge time and

the capability to randomly change column addresses

on each clock cycle during a burst access.

GENERAL DESCRIPTION

The 64Mb SDRAM is a high-speed CMOS, dynamic

random-access memory containing 67,108,864-bits. It

is internally configured as a quad-bank DRAM with a

synchronous interface (all signals are registered on the

positive edge of the clock signal, CLK). Each of the

16,777,216-bit banks is organized as 2,048 rows by 256

columns by 32 bits.

Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a pro-

grammed sequence. Accesses begin with the registra-

tion of an ACTIVE command, which is then followed by

a READ or WRITE command. The address bits regis-

tered coincident with the ACTIVE command are used

to select the bank and row to be accessed (BA0, BA1

select the bank, A0-A10 select the row). The address

bits registered coincident with the READ or WRITE com-

mand are used to select the starting column location

for the burst access.

64Mb (x32) SDRAM PART NUMBER

PART NUMBER

ARCHITECTURE

MT48LC2M32B2TG

2 Meg x 32

MT48LC2M32B2 Datasheet(PDF) 2 Page - Micron Technology

MT48LC2M32B2 Datasheet(HTML) 2 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL