Z86C2116FSC datasheet(17/35 Pages) ZILOG

17 / 35 page

Z86C21 MCU

WITH

8K ROM

Clock. The Z86C21 on-chip oscillator has a high-gain,

parallel-resonant amplifier for connection to a crystal, LC,

ceramic resonator, or any suitable external clock source

(XTAL1 = Input, XTAL2 = Output). The crystal should be AT

cut, 1 MHz to 16 MHz max, and series resistance (RS) is

less than or equal to 100 Ohms. The crystal should be

connected across XTAL1 and XTAL2 using the recom-

mended capacitors (10 pF < CL < 300 pF) from each pin

11, ground instead of just system ground. This prevents

noise injection into the clock input (Figure 17).

Note: Actual capacitor value is specified by the crystal

manufacturer.

Figure 17. Oscillator Configuration

XTAL1

XTAL2

XTAL1

XTAL2

XTAL1

XTAL2

Ceramic Resonator

or Crystal

LC Clock

External Clock

Pin 11

HALT. Turns off the internal CPU clock but not the XTAL

oscillation. The counter/timers and the external interrupts

IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The device

is recovered by interrupts, either externally or internally

generated. An interrupt request must be executed (en-

abled) to exit HALT mode. After the interrupt service

routine, the program continues from the instruction after

the HALT.

STOP. This instruction turns off the internal clock and

external crystal oscillation and reduces the standby cur-

rent to 5

µA (typical) or less. The STOP mode is terminated

by a reset which causes the processor to restart the

application program at address 000C (HEX).

In order to enter STOP (or HALT) mode, it is necessary to

first flush the instruction pipeline to avoid suspending

execution in mid-instruction. To do this, the user must

execute a NOP (opcode=0FFH) immediately before the

appropriate sleep instruction. i.e.,

FF NOP

; clear the pipeline

6F STOP

; enter STOP mode

FF NOP

; clear the pipeline

7F HALT

; enter HALT mode

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