AX88796LF datasheet(24/71 Pages) ASIX

24 / 71 page

ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

buffer address does not match either the Boundary Pointer or Page Stop Address, the link to the next buffer is

performed.

LINKING BUFFERS

Before the DMA can enter the next contiguous 256 bytes buffer, the address is checked for equality to PSTOP

and to the Boundary Pointer. If neither are reached, the DMA is allowed to use the next buffer.

BUFFER RING OVERFLOW

If the Buffer Ring has been filled and the DMA reaches the Boundary Pointer Address, reception of the incoming

packet will be aborted by the AX88796. Thus, the packets previously received and still contained in the Ring will

not be destroyed. In a heavily loaded network environment the local DMA may be disabled, preventing the

AX88796 from buffering packets from the network. To guarantee this will not happen, a software reset must be

issued during all Receive Buffer Ring over flows (indicated by the OVW bit in the Interrupt Status Register).

The following procedure is required to recover from a Receiver Buffer Ring Overflow. If this routine is not

adhered to, the AX88796 may act in an unpredictable manner. It should also be noted that it is not permissible to

service an overflow interrupt by continuing to empty packets from the receive buffer without implementing the

prescribed overflow routine.

Note: It is necessary to define a variable in the driver, which will be called ``Resend''.

1. Read and store the value of the TXP bit in the AX88796's Command Register.

2. Issue the STOP command to the AX88796. This is accomplished be setting the STP bit in the AX88796's

Command Register. Writing 21H to the Command Register will stop the AX88796.

3. Wait for at least 1.5 ms. Since the AX88796 will complete any transmission or reception that is in progress,

it is necessary to time out for the maximum possible duration of an Ethernet transmission or reception. By

waiting 1.5 ms this is achieved with some guard band added. Previously, it was recommended that the RST bit

of the Interrupt Status Register be polled to insure that the pending transmission or reception is completed.

This bit is not a reliable indicator and subsequently should be ignored.

4. Clear the AX88796's Remote Byte Count registers (RBCR0 and RBCR1).

5. Read the stored value of the TXP bit from step 1, above. If this value is a 0, set the ``Resend'' variable to a 0

and jump to step 6. If this value is a 1, read the AX88796's Interrupt Status Register. If either the Packet

Transmitted bit (PTX) or Transmit Error bit (TXE) is set to a 1, set the ``Resend'' variable to a 0 and jump to

step 6. If neither of these bits is set, place a 1 in the ``Resend'' variable and jump to step 6. This step determines

if there was a transmission in progress when the stop command was issued in step 2. If there was a

transmission in progress, the AX88796's ISR is read to determine whether or not the packet was recognized by

the AX88796. If neither the PTX nor TXE bit was set, then the packet will essentially be lost and retransmitted

only after a time-out takes place in the upper level software. By determining that the packet was lost at the

driver level, a transmit command can be reissued to the AX88796 once the overflow routine is completed (as

in step 11). Also, it is possible for the AX88796 to defer indefinitely, when it is stopped on a busy network.

Step 5 also alleviates this problem. Step 5 is essential and should not be omitted from the overflow routine, in

order for the AX88796 to operate correctly.

6. Place the AX88796 in mode 1 loopback. This can be accomplished by setting bits D2 and D1, of the Transmit

Configuration Register to ``0,1''.

7. Issue the START command to the AX88796. This can be accomplished by writing 22H to the Command

8. Remove one or more packets from the receive bufferring.

9. Reset the overwrite warning (OVW, overflow) bit in the Interrupt Status Register.

10. Take the AX88796 out of loopback. This is done by writing the Transmit Configuration Register with the

value it contains during normal operation. (Bits D2 and D1 should both be programmed to 0.)

11. If the ``Resend'' variable is set to a 1, reset the ``Resend'' variable and reissue the transmit command. This is

done by writing a value of 26H to the Command Register. If the ``Resend'' variable is 0, nothing needs to

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