AX88796LF datasheet(38/71 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88796 L

3-in-1 Local Bus Fast Ethernet Controller

5.1.14 Test Register (TR) Offset 15H (Read)

FIELD

NAME

DESCRIPTION

7:4

Reserved

RST_TX

100BASE-TX in Reset : This signal indicates that 100BASE-TX logic of internal PHY is

in reset.

RST_10B 10BASE-T in Reset : This signal indicates that 10BASE-T logic of internal PHY is in reset.

RST_B Reset Busy : This signal indicates that internal PHY is in reset.

AUTOD Autonegotiation Done : This signal goes high whenever internal PHY autonegotiation has

completed. It will go low if autonegotiation has to restart.

5.1.15 General Purpose Input Register (GPI) Offset 17H (Read)

FIELD

NAME

DESCRIPTION

Reserved

GPI2

This register reflects GPI[2] input value. May connect to external PHY speed status.

GPI1

This register reflects GPI[1] input value. May connect to external PHY duplex status.

GPI0

This register reflects GPI[0] input value. May connect to external PHY link status.

Reserved

I_SPD

This register reflects internal PHY speed status value. Logic one means 100Mbps

I_DPX

This register reflects internal PHY duplex status value. Logic one means full duplex.

I_LINK This register reflects internal PHY link status value. Logic one means link ok.

5.1.16 GPO and Control (GPOC) Offset 17H (Write)

FIELD

NAME

DESCRIPTION

Reserved

PPDSET Internal PHY Power Down Setting:

Default “0”, Internal PHY is in normal operation mode

Write PPDSET to “1” force Internal PHY into power down mode

MPSET Media Set by Program : The signal is valid only when MPSEL is set to high.

When MPSET is logic 0 , internal PHY is selected.

When MPSET is logic 1 , external MII PHY is selected.

MPSEL Media Priority Select :

MPSEL

I_LINK

GPI0

Media Selected

Internal PHY

External MII PHY

Internal PHY

Depend on MPSET bit

3:1

Reserved

/GPO0

Default “0”. The register reflects to GPO[0] pin with inverted value.

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