BQ76PL536APAPR datasheet(5/74 Pages) TI1

5 / 74 page

bq76PL536A

www.ti.com

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

Host-to-device interface – initiates a synchronous conversion. Pin has 250-nA internal

CONV_H

sink to VSS.

CONV_N

Current-mode output to the next-higher bq76PL536A to initiate a conversion

CONV_S

Input from the adjacent lower bq76PL536A to initiate a conversion

CS_H

Host-to-device interface – active-low chip select from host. Internal 100-k

Ω pullup resistor

CS_N

Current-mode output used to select the next-higher bq76PL536A for SPI communication

CS_S

Current-mode input SPI chip-select (slave-select) from the next-lower bq76PL536A

DRDY_H

Host-to-device interface – conversion complete, data-ready indication

DRDY_N

Current-mode input indicating conversion data is ready from next-higher bq76PL536A

DRDY_S

Current-mode output indicating conversion data is ready to the next lower bq76PL536A

FAULT_H

Host-to-device interface – FAULT condition detected in this or higher (North) device

FAULT_N

Current-mode input indicating a system status change from the next-higher bq76PL536A

FAULT_S

Current-mode output

GPAI+

General-purpose (differential) analog input, connect to VSS if unused.

GPAI–

General-purpose (differential) analog input, connect to VSS if unused.

GPIO

IOD

Digital open-drain I/O. A 10-k

Ω to 2-MΩ pullup is recommended.

HSEL

Host interface enable, 0 = enable, 1 = disable

LDOA

Internal analog 5-V LDO bypass connection, requires 2.2-µF ceramic capacitor for stability

Internal digital 5-V LDO bypass connection 1, requires 2.2-µF ceramic capacitor for

LDOD1

stability. This pin is tied internally to LDOD2. This pin should be tied to LDOD2 externally.

Internal digital 5-V LDO bypass connection 2, requires 2.2-µF ceramic capacitor for

LDOD2

stability. This pin is tied internally to LDOD1. This pin should be tied to LDOD1 externally.

NC30

–

No connection

NC51

–

No connection

NC62

–

No connection

REG50

5-V user LDO output, requires 2.2-µF ceramic capacitor for stability

SCLK_H

Host-to-device interface – SPI clock from host

SCLK_N

Current-mode output SPI clock to the next-higher bq76PL536A

SCLK_S

Current-mode input SPI clock from the next-lower bq76PL536A

SDI_H

Host-to-device interface – data from host to device (host MOSI signal)

SDI_N

Current-mode output for SPI data to the next-higher bq76PL536A

SDI_S

Current-mode input for SPI data from the next-lower bq76PL536A

Host-to-device interface – data from device to host (host MISO signal), 3-state pin, 250-nA

SDO_H

internal pullup

SDO_N

Current-mode input for SPI data from the next-lower bq76PL536A

SDO_S

Current-mode output for SPI data to the next-lower bq76PL536A

Factory test pin. Connect to VSS in user circuitry. This pin includes an approximately100-

TEST

Ω internal pulldown

TS1+

Differential temperature sensor input

TS1–

Differential temperature sensor input

TS2+

Differential temperature sensor input

TS2–

Differential temperature sensor input

VC0

Sense-voltage input terminal for negative terminal of first cell (VSS)

VC1

Sense voltage input terminal for positive terminal of the first cell

VC2

Sense voltage input terminal for the positive terminal of the second cell

VC3

Sense voltage input terminal for the positive terminal of the third cell

VC4

Sense voltage input terminal for the positive terminal of the fourth cell

VC5

Sense voltage input terminal for the positive terminal of the fifth cell

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