BQ76PL536APAPR datasheet(9/74 Pages) TI1

9 / 74 page

bq76PL536A

www.ti.com

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

Electrical Characteristics (continued)

Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40°C to 85°C and VBAT = 7.2 V

to 27 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

HOST INTERFACE

Logic-level output

voltage, high; SDO_H,

VOH

CL = 20 pF, IOH < 5 mA

(1)

4.5

VLDOD

FAULT_H, ALERT_H,

DRDY

Logic-level output

voltage, low; SDO_H,

VOL

CL = 20 pF, IOL < 5 mA

(1)

VSS

0.5

FAULT_H, ALERT_H,

DRDY

Logic-level input voltage,

VIH

high; SCLK_H, SDI_H,

5.2

CS_H, CONV

Logic-level input voltage,

VIL

low; SCLK_H, SDI_H,

VSS

0.8

CS_H, CONV

Input capacitance

CIN

SCLK_H, SDI_H, CS_H,

CONV

Input leakage current

ILKG

SCLK_H, SDI_H, CS_H,

µA

CONV

GENERAL PURPOSE INPUT/OUTPUT (GPIO)

Logic-level input voltage,

VIH

Vin

≤ VREG50

high

Logic-level input voltage,

VIL

0.8

low

Output high-voltage

VOH

Supplied by external approximately100-k

Ω resistor

VREG50

pullup voltage

Logic-level output

VOL

IOL = 1 mA

0.3

voltage, low

CIN

Input capacitance(1)

ILKG

Input leakage current

µA

CELL BALANCING CONTROL OUTPUT (CBx)

CBz

Output impedance

1 V < VCELL < 5 V

100

120

VRANGE

Output V

VCn-1

VCn

ADC COMMON SPECIFICATIONS

ADC_CONTROL[ADC_ON] = 1

5.4

6.6

µs

CONV high to

tCONV_START

conversion start(2) (3)

ADC_CONTROL[ADC_ON] = 0

500

µs

Conversion time per

tCONV

ADC_CONTROL[ADC_ON] = 1

5.4

6.6

µs

selected channel(4)

ILKG

Input leakage current

Not converting

<10

100

VCn (CELL) INPUTS

VIN

Input voltage range(5)

VCn – VCn–1, where n = 1 to 6

VRES

Voltage resolution(6)

14 bits

~378

µV

Voltage accuracy, total

–10°C

≤ TA ≤ 50°C, 1.2 V < VIN < 4.5 V

–5

±1

VACC

error,

–40°C

≤ TA ≤ 85°C, 1.2 V < VIN < 4.5 V

–8

VIN = VCn to VCn–1

(1)

Total simultaneous current drawn from all pins is limited by LDOD current to

≤10 mA.

(2)

If ADC_CONTROL[ADC_ON] = 0, add 500 µs to conversion time to allow ADC subsystem to stabilize. This is self-timed by the part.

(3)

Additional 50 ms (POR) is required before first conversion after a) initial cell connection; or b) VBAT falls below VPOR.

(4)

Plus tCONV_START,that is, if device is programmed for six channel conversions, total time is approximately 6 × 6 + 6 = 42 µs.

(5)

0 V may not lie within the range of measured values due to offset voltage limit and device calibration.

(6)

See text for specific conversion formula.

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