ADC0852 datasheet(9/20 Pages) NSC

9 / 20 page

Functional Description

1 1 The Sampled-data Comparator

The ADC0852 and ADC0854 utilize a sampled-data com-

parator structure to compare the analog difference between

a selected ‘‘a’’ and ‘‘b’’ input to an 8-bit programmable

threshold

This comparator consists of a CMOS inverter with a capaci-

tively coupled input (

Figure 4 ) Analog switches connect the

two comparator inputs to the input capacitor and also con-

nect the inverter’s input and output This device in effect

now has one differential input pair A comparison requires

two cycles one for zeroing the comparator and another for

making the comparison

FIGURE 4 Sampled-Data Comparator

In the first cycle (

Figure 4a ) one input switch and the invert-

er’s feedback switch are closed In this interval the input

capacitor (C) is charged to the connected input (V1) less the

inverter’s bias voltage (VB approx 12 volts) In the second

cycle (

Figure 4b ) these two switches are opened and the

other (V2) input’s switch is closed The input capacitor now

subtracts its stored voltage from the second input and the

difference is amplified by the inverter’s open loop gain The

inverter input (VB’) becomes VB b (V1 b V2)

C a CS

and

the output will go high or low depending on the sign of VB’-

TLH5521 – 8

FIGURE 4a Zeroing Phase

V0 e VB

VonC e V1–VB

CS e Stray Input Node Cap

VB e Inverter Input Bias Voltage

TLH5521 – 9

FIGURE 4b Compare Phase

VB bVB e (V2bV1)

CaCS

V0 e

Ca CS

CV2bCV1

V0 is dependent on V2bV1

TLH5521 – 14

V0 e

C1 a C2 a CS

C1 (V2 b V1) a C2 (V4 b V3)

C1 a C2 a CS

QC1 a D QC2

Comparator Reads VTH from Internal DAC Differentially

FIGURE 4c Multiple Differential Inputs

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